Instruction and logic for parallel multi-step power management flow

Patent metadata

Field	Value
Publication number	US-11016556-B2
Application number	US-201916513267-A
Country	US
Kind code	B2
Filing date	Jul 16, 2019
Priority date	Dec 9, 2016
Publication date	May 25, 2021
Grant date	May 25, 2021

Abstract

A parallel multi-step power management flow apparatus and method for using the same are disclosed. In one embodiment, an integrated circuit comprises a plurality of processing entities to execute operations, a power controller coupled to the plurality of processing entities to control power management for the plurality of processing entities, and a plurality of agents, where each of the plurality of agents is operable to perform a power control flow for one of the processing entities by separately scheduling, using a scheduler, and executing a plurality of power control flow phases in response to a plurality of requests received from the power controller, and each agent is operable to send a plurality of acknowledgements, one acknowledgement for each phase, upon completion of the plurality of power control flow phases.

First claim

What is claimed is:

1. A system-on-chip (SoC) comprising:
a plurality of processing entities to execute operations;
a power controller coupled to the plurality of processing entities to control power management for the plurality of processing entities; and
a plurality of agents, each of the plurality of agents to perform a power control flow for one of the processing entities by separately scheduling, using a scheduler, and executing a plurality of power control flow phases in response to the power controller requesting the plurality of power control flow phases be performed, said each agent operable to send a plurality of acknowledgements, one acknowledgement for each phase, upon completion of the plurality of power control flow phases, wherein each agent comprises circuitry to perform the power control flow for its associated processing entity according to a plurality of processing logics, each of the processing logics to specify operations for one phase of the power control flow, and further wherein each agent accesses the processing logics and schedules the operations specified by the processing logics in response to receiving the plurality of requests from the power controller.

2. The SoC defined in claim 1 wherein the plurality of processing entities comprises at least one core.

3. The SoC defined in claim 1 wherein the plurality of processing entities comprises a memory controller.

4. The SoC defined in claim 1 wherein each of the plurality of agents is operable to send acknowledgements in parallel indicating phases of plurality of power control flow phases have been completed only after all of the plurality of power control flow phases have been completed.

5. The SoC defined in claim 1 wherein at least one of the plurality of agents is operable to send at least one of the acknowledgements indicating completion of one or more of the plurality of phases that were not performed for its associated processing entity due to the one or more phases not being relevant to the processing entity.

6. The SoC defined in claim 1 wherein the plurality of processing logics set forth operations to transition one of the processing entities into and out of a C6 power state.

7. The SoC defined in claim 1 wherein the plurality of processing logics set forth operations to enable one of the processing entities to undergo voltage and frequency scaling.

8. The SoC defined in claim 1 wherein the plurality of processing logics comprises:
a first processing logic to specify operations associated with placing the core in a quiesced state;
a second processing logic to specify operations associated with blocking one or more interfaces to the core;
a third processing logic to specify operations associated with stopping core clocking;
a fourth processing logic to specify operations associated with exiting a reduced power consumption state in which the core resides; and
a fifth processing logic to specify operations associated with causing the core to resume executing instructions.

9. The SoC defined in claim 1 wherein each of the plurality of agents is operable to perform the power control flow in response to a plurality of requests sent within a single message from the power controller, each request of the plurality of requests for requesting performance of one of the plurality of power control flow phases.

10. A processor comprising:
a plurality of cores to execute operations and a memory controller;
a power controller coupled to the plurality of processing entities, including a plurality of core and a memory controller to control power management for the plurality of processing entities; and
a plurality of agents, each of the plurality of agents to perform a power control flow for one of the plurality of cores and the memory controller, each agent comprising
a scheduler operable to separately schedule a plurality of power control flow phases in response to requesting from the power controller to perform the power control flow phases, and
circuitry to perform a plurality of processing logics that specify operations for the power control flow for its associated processing entity, each of the plurality of processing logics to specify operations for one phase of the power control flow, and further wherein each agent is operable to access the processing logics and use the scheduler to schedule operations specified by the processing logics in response to the requesting from the power controller, and
said each agent operable to send a plurality of acknowledgements, one acknowledgement for each phase, upon completion of the plurality of power control flow phases.

11. The processor defined in claim 10 wherein each of the plurality of agents is operable to send acknowledgements in parallel indicating phases of plurality of power control flow phases have been completed only after all of the plurality of power control flow phases have been completed.

12. The processor defined in claim 10 wherein at least one of the plurality of agents is operable to send at least one of the acknowledgements indicating completion of one or more of the plurality of phases that were not performed for its associated processing entity due to the one or more phases not being relevant to the processing entity.

13. The processor defined in claim 10 wherein the plurality of processing logics set forth operations to transition one of the processing entities into and out of a C6 power state and to undergo voltage and frequency scaling.

14. A system comprising:
an interconnect;
a dynamic random-access memory (DRAM) coupled to the interconnect; and
a processor coupled the interconnect, including
a plurality of processing entities to execute operations,
a power controller coupled to the plurality of processing entities to control power management for the plurality of processing entities, and
a plurality of agents, each of the plurality of agents to perform a power control flow for one of the processing entities by separately scheduling, using a scheduler, and executing a plurality of power control flow phases in response to the power controller requesting the plurality of power control flow phases be performed, said each agent operable to send a plurality of acknowledgements, one acknowledgement in each phase, upon completion of the plurality of power control flow phases, wherein each agent comprises circuitry to perform the power control flow for its associated processing entity according to a plurality of processing logics, each of the processing logics to specify operations for one phase of the power control flow, and further wherein each agent accesses the processing logics and schedules the operations specified by the processing logics in response to receiving the plurality of requests from the power controller.

15. The system defined in claim 14 wherein the plurality of processing entities comprises at least one core.

16. The system defined in claim 14 wherein each of the plurality of agents is operable to send acknowledgements indicating phases of plurality of power control flow phases have been completed only after all of the plurality of power control flow phases have been completed.

17. The system defined in claim 14 wherein at least one of the plurality of agents is operable to send at least one of the acknowledgements indicating completion of one or more of the plurality of phases that were not performed for its associated processing entity due to the one or more phases not being relevant to the processing entity.

18. The system defined in claim 14 wherein the plurality of process

Assignees

• Intel Corp

Inventors

• Gendler Alexander
• Rajwan Doron
• Kuzi Tal
• Mulla Dean
• Szapiro Ariel
• Tell Nir

Classifications

• G06F1/329

  by task scheduling · CPC title

• G06F1/3206

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F1/3243 Primary

  Power saving in microcontroller unit · CPC title

• G06F1/3296 Primary

  by lowering the supply or operating voltage · CPC title