Interface for power systems

US11016452B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11016452-B2
Application numberUS-201916280711-A
CountryUS
Kind codeB2
Filing dateFeb 20, 2019
Priority dateFeb 20, 2018
Publication dateMay 25, 2021
Grant dateMay 25, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A controller hardware in the loop (CHIL) interface is disclosed. The CHIL interface comprises software and hardware that redirects a signal flow, including modulation signals and measurements exchanged between controller logic and a power electronics converter (PEC), to a CHIL port. Accordingly, the CHIL port provides access to the controller logic, at a digital level, throughout phases of the controller's lifetime (i.e., design, installation, maintenance, upgrade). Thus, the CHIL interface facilitates the use of PEC simulators for testing. The CHIL interface can detach the actual PEC from the control logic so testing can be performed with or without an operating PEC and can avoid the need for dedicated and error prone signal conditioning circuitry that is external to the controller.

First claim

Opening claim text (preview).

The invention claimed is: 1. A power conversion system comprising: a power electronics converter (PEC) that is configurable to convert electrical energy from one form to another; a controller connected to the PEC that controls operation of the PEC, wherein the controller comprises: a processor; a controller hardware in loop (CHIL) port; and a CHIL interface that is configurable to couple the processor to the CHIL port (i) instead of the PEC or (ii) in addition to the PEC; a PEC simulator connected to the CHIL port and a computer connected to the PEC simulator and/or the CHIL port, wherein the PEC simulator simulates the operation of the PEC in response to digital signals from the processor, wherein the computer is configured to test the PEC and/or the controller using the PEC simulator, said test comprising: configuring the CHIL interface to couple the processor to the CHIL port and the PEC so that control signals from the processor for the PEC are also received at the CHIL port, and (a) comparing a first response from the PEC to a second response from the PEC simulator, wherein the first and second responses correspond to the same control signal from the processor for controlling the PEC; or (b) comparing a response from the PEC simulator to a known value, wherein the response corresponds to a control signal from the processor for controlling the PEC simulator. 2. The power conversion system according to claim 1 , wherein the CHIL port is integrated with the controller so that the computer and/or the PEC simulator may be connected to or disconnected from the CHIL port at any point during the operational lifetime of the controller without altering the connection between the controller and the PEC. 3. A method for testing a power conversion system, the method comprising: providing a power conversion system comprising a controller and a power electronics converter (PEC), wherein the controller comprises a controller hardware in loop (CHIL) interface that is configurable to couple a processor of the controller to a CHIL port on the controller (i) instead of the PEC or (ii) in addition to the PEC; connecting a PEC simulator to the CHIL port; configuring the CHIL interface to couple the processor to the CHIL port and the PEC so that control signals from the processor for the PEC are also received at the CHIL port; and comparing a first response from the PEC to a second response from the PEC simulator to test the power conversion system, wherein the first and second responses correspond to the same control signal from the processor for controlling the PEC. 4. A method for testing a power conversion system, the method comprising: providing a power conversion system comprising a controller and a power electronics converter (PEC), wherein the controller comprises a controller hardware in the loop (CHIL) interface that is configurable to couple a processor of the controller to a CHIL port on the controller (i) instead of the PEC or (ii) in addition to the PEC; connecting a PEC simulator to the CHIL port; configuring the CHIL interface to couple the processor to the CHIL port and decouple the processor from the PEC so that control signals from the processor are only received at the CHIL port; and comparing a response from the PEC simulator to a known value to test the power conversion system, wherein the response corresponds to a control signal from the processor for controlling the PEC simulator. 5. The method according to claim 4 , wherein the CHIL port is integrated with the controller so that the PEC simulator may be connected to or disconnected from the CHIL port at any point during the operational lifetime of the controller without altering the connection between the controller and the PEC. 6. The method according to claim 4 , further comprising: connecting a computer connected to the CHIL port and/or the PEC simulator. 7. The method according to claim 6 further comprising: performing the operations of configuring and comparing at the computer. 8. A controller that controls the operation of a power electronics converter (PEC) in a power conversion system, the controller comprising: a processor; a controller hardware in loop (CHIL) port; and a CHIL interface that is configurable to couple the processor to the CHIL port (i) instead of the PEC or (ii) in addition to the PEC; wherein the CHIL port is integrated with the controller so that a computer and/or a PEC simulator may be connected to or disconnected from the CHIL port at any point during the operational lifetime of the controller without altering the connection between the controller and the PEC, wherein when the PEC simulator is connected to the CHIL port, the PEC simulator simulates the operation of the PEC in response to digital signals from the processor, and wherein when a computer is connected to the CHIL port and/or the PEC simulator, the computer is configured to test the PEC and/or the controller using the PEC simulator. 9. The controller according to claim 8 , wherein the test of the PEC and/or the controller comprises: configuring the CHIL interface to couple the processor to the CHIL port and the PEC so that control signals from the processor for the PEC are also received at the CHIL port; and comparing a first response from the PEC to a second response from the PEC simulator, wherein the first and second responses correspond to the same control signal from the processor for controlling the PEC. 10. The controller according to claim 9 , wherein the test of the system for converting power comprises: configuring the CHIL interface to couple the processor to the CHIL port and decouple the processor from the PEC so that control signals from the processor are only received at the CHIL port; and comparing a response from the PEC simulator to a known value, wherein the response corresponds to a control signal from the processor for controlling the PEC simulator.

Assignees

Inventors

Classifications

  • Input/output · CPC title

  • G05B17/02Primary

    electric · CPC title

  • HIL hardware in the loop, simulates equipment to which a control module is fixed · CPC title

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Frequently asked questions

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What does patent US11016452B2 cover?
A controller hardware in the loop (CHIL) interface is disclosed. The CHIL interface comprises software and hardware that redirects a signal flow, including modulation signals and measurements exchanged between controller logic and a power electronics converter (PEC), to a CHIL port. Accordingly, the CHIL port provides access to the controller logic, at a digital level, throughout phases of the …
Who is the assignee on this patent?
Univ Florida State Res Found Inc
What technology area does this patent fall under?
Primary CPC classification G05B19/0423. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue May 25 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).