Testing integrated circuit designs containing multiple phase rotators

Patent metadata

Field	Value
Publication number	US-11016144-B2
Application number	US-202016739406-A
Country	US
Kind code	B2
Filing date	Jan 10, 2020
Priority date	Jan 15, 2014
Publication date	May 25, 2021
Grant date	May 25, 2021

Abstract

Approaches for testing phase rotators are provided. A circuit for testing phase rotators includes a compare element including a first input and a second input, wherein the compare element is configured to compare a first phase of a first signal provided at the first input to a second phase of a second signal provided at the second input. The circuit also includes a first test bus connected to the first input and a second test bus connected to the second input.

First claim

What is claimed is:

1. A circuit, comprising:
a plurality of phase rotators; and
a compare element,
wherein the circuit is configured to:
connect a first phase source to a first input of the compare element;
connect a second phase source to a second input of the compare element, wherein the second phase source comprises an output of one of the plurality of phase rotators that are selectively connectable to the second input;
generate an expected value of a phase relationship between the first phase source and the second phase source; and
compare the expected value to an output of the compare element.

2. The circuit of claim 1 , wherein the first phase source comprises one of:
an output of another one of the plurality of phase rotators; and
an output of a phase locked loop.

3. The circuit of claim 1 , wherein the circuit is further configured to:
select at least one of a first phase and a first weight for the first phase source; and
select at least one of a second phase and a second weight for the second phase source.

4. The circuit of claim 1 , wherein the circuit is configured to repeat the connecting the second phase source, the generating, and the comparing for each one of the plurality of phase rotators.

5. The circuit of claim 1 , wherein the compare element comprises a tunable AND gate.

6. The circuit of claim 5 , wherein the circuit is further configured to provide a control signal to control the tunable AND gate, wherein the control signal provides timing control.

7. The circuit of claim 5 , wherein the circuit is further configured to provide a control signal to control the tunable AND gate, wherein the control signal provides minimum pulse width control.

8. The circuit of claim 5 , wherein the circuit is further configured to provide a control signal to control the tunable AND gate, wherein the control signal provides dead-band control.

9. The circuit of claim 1 , wherein the compare element comprises a phase detector.

10. The circuit of claim 9 , wherein the circuit is further configured to provide other inputs to the phase detector that determines sensitivity of the phase detector.

11. The circuit of claim 9 , wherein the circuit is further configured to provide other inputs to the phase detector that determines dead-band of the phase detector.

12. The circuit of claim 1 , wherein the circuit is further configured to log a pass or a fail based on the comparing the expected value to the output of the compare element.

13. The circuit of claim 1 , wherein the connecting the second phase source comprises controlling a plurality of switches to:
select one of the plurality of switches to connect the one of the plurality of phase rotators to the second input of the compare element; and
not select others of the plurality of switches to disconnect the plurality of phase rotators, other than the one of the plurality of phase rotators connected to the second input of the compare element.

14. The circuit of claim 1 , wherein the first phase source comprises an output of a phase locked loop (PLL) that is separate from the plurality of phase rotators and that is selectively connected to, and disconnected from, the first input using a switch.

15. The circuit of claim 14 , wherein the circuit is further configured to:
provide the output of the PLL as input to a test phase rotator; and
provide an output of the test phase rotator as input to the PLL.

16. The circuit of claim 1 , wherein:
the compare element receives a control signal separate from the first input and the second input; and
the compare element comprises tunable logic, and the control signal provides control to the tunable logic including one of: timing control; minimum pulse width control; and dead-band control.

17. A circuit, comprising:
a plurality of phase rotators; and
a compare element,
wherein the circuit is configured to:
connect a first phase source to a first input of the compare element, wherein the first phase source comprises an output of one of the plurality of phase rotators that are selectively connectable to the first input;
connect a second phase source to a second input of the compare element, wherein the second phase source comprises an output of another one of the plurality of phase rotators that are selectively connectable to the second input;
generate an expected value of a phase relationship between the first phase source and the second phase source;
compare the expected value to an output of the compare element; and
log a pass or a fail based on the comparing the expected value to the output of the compare element.

18. The circuit of claim 17 , wherein the circuit is further configured to provide a control signal to the compare element, wherein:
the control signal is separate from the first input and the second input,
the control signal provides control to tunable logic of the compare element, and
the control includes one of: timing control; minimum pulse width control; and dead-band control.

19. A circuit, comprising:
a plurality of phase rotators; and
a compare element,
wherein the circuit is configured to:
connect an output of a first one of the plurality of phase rotators to a first input of the compare element;
connect an output of a second one of the plurality of phase rotators to a second input of the compare element;
generate an expected value of a phase relationship between the output of the first one of the plurality of phase rotators and the output of the second one of the plurality of phase rotators;
compare the expected value to an output of the compare element; and
determine a pass or a fail based on the comparing.

20. The circuit of claim 19 , wherein the circuit is further configured to provide a control signal to the compare element, wherein:
the control signal is separate from the first input and the second input,
the control signal provides control to tunable logic of the compare element, and
the control includes one of: timing control; minimum pulse width control; and dead-band control.

Assignees

• IBM

Inventors

• Gerowitz Robert G
• Higgins Sarah B
• Iadanza Joseph A

Classifications

• G01R25/005 Primary

  Circuits for comparing several input signals and for indicating the result of this comparison, e.g. equal, different, greater, smaller, or for passing one of the input signals as output signal · CPC title

• H04L7/042

  Detectors therefor, e.g. correlators, state machines (digital correlators in general G06F17/15) · CPC title

• G01R31/31703

  Comparison aspects, e.g. signature analysis, comparators (concerning scan tests G01R31/318566; concerning testers G01R31/3193) · CPC title

• G01R29/18

  Indicating phase sequence; Indicating synchronism · CPC title

• G06F30/36

  Circuit design at the analogue level · CPC title