Oversampling digital receiver for radio-frequency signals

Patent metadata

Field	Value
Publication number	US-11012960-B2
Application number	US-201816102312-A
Country	US
Kind code	B2
Filing date	Aug 13, 2018
Priority date	Oct 4, 2005
Publication date	May 18, 2021
Grant date	May 18, 2021

Abstract

A system and method for receiving a radio frequency signal, comprising a device for digitizing, without prior alteration of frequency, an analog radio frequency representation of each of a plurality of radio frequency signals to produce a respective plurality of digital radio frequency signals having a respective associated radio frequency digital clock, the plurality of digital radio frequency signals having a sufficiently high respective associated clock rate to preserve an information content of an information communication present in the analog radio frequency representation; a switch matrix adapted to concurrently switch the plurality of digital radio frequency signals and associated digital radio frequency clock to ones of a plurality of digital signal processors; and a control adapted to selectively automatically control the concurrent switching of a plurality of digital signals and associated digital clock to the respective plurality of digital signal processors; wherein the digital signal processors produce processed representations of information contained in respective analog radio frequency representations.

First claim

What is claimed is:

1. A radio system, comprising:
a plurality of radio frequency output ports;
a plurality of radio frequency input ports;
a plurality of digital-to-analog converters, configured to convert a plurality of digital signals to corresponding radio frequency analog signals at the plurality of radio frequency ports;
a plurality of analog-to-digital converters, configured to convert a plurality of analog radio frequency signals to a plurality of digital information streams;
a digital baseband processor, configured to concurrently process the plurality of digital signals; and
a non-blocking switch matrix, configured to concurrently selectively switch signals from the digital baseband processor to the plurality of digital-to-analog converters and to concurrently selectively switch signals to the digital baseband processor from the plurality of analog-to-digital converters, without preceding signal downconversion.

2. The radio system according to claim 1 , wherein the non-blocking switch matrix comprises at least one non-blocking n×m switch matrix, where n and m are each at least 4.

3. The radio system according to claim 1 , wherein the non-blocking switch matrix is configured to receive a plurality of digitized signals which have respectively asynchronous digital clocks, and to switch the plurality of digitized signals together with their respective asynchronous digital clocks.

4. The radio system according to claim 1 , further comprising a digital channelizer, configured to generate a sub-band from a respective digital modulated information stream by at least one of digital mixing and digital filtering of the respective digital signals.

5. The radio system according to claim 1 , wherein the non-blocking switch matrix is configured to multicast.

6. A radio system, comprising:
a plurality of input ports, configured to receive a plurality of analog radio frequency signals;
a plurality of analog-to-digital converters, configured to convert the plurality of received analog signals to a plurality of digital stream representations of the analog radio frequency signals;
a plurality of digital-to-analog converters, configured to convert the plurality of digital information streams to produce a plurality of analog signals;
a plurality of radio frequency output ports, configured to output a plurality of radio frequency signals corresponding to the plurality of analog signals;
a non-blocking switch matrix, configured to concurrently selectively switch signals corresponding to the plurality of digital information streams to the plurality of digital-to-analog converters and to concurrently selectively switch signals corresponding to the respective digital stream representations of the analog radio frequency signals from the plurality of analog-to-digital converters without preceding signal downconversion; and
a digital baseband processor, configured to:
concurrently process the plurality of digital information streams for conversion by the plurality of digital-to-analog converters, and
concurrently process at least two of the plurality of digital stream representations of the analog radio frequency signals digital information streams from the plurality of analog-to-digital converters.

7. The radio system according to claim 6 , wherein the non-blocking switch matrix is configured to switch digitized signals which are upconverted from baseband.

8. The radio system according to claim 6 , wherein the non-blocking switch matrix comprises at least one non-blocking n×m switch matrix, where n and m are each at least 4.

9. The radio system according to claim 6 , wherein the non-blocking switch matrix is configured to receive a plurality of digitized signals which have respectively asynchronous digital clocks, and to switch the plurality of digitized signals together with their respective asynchronous digital clocks.

10. The radio system according to claim 6 , wherein the non-blocking switch matrix is configured to multicast.

11. A radio system, comprising:
a plurality of analog radio frequency output ports configured to transmit a plurality of outbound analog radio frequency signals;
a plurality of analog radio frequency input ports configured to receive a plurality of inbound analog radio frequency signals;
a first converter configured to convert a first plurality of radio frequency signals between a plurality of outbound digital stream representations to respective outbound analog representations thereof for communication through the plurality of analog radio frequency output ports;
a second converter configured to convert a second plurality of radio frequency signals between a plurality of inbound analog representations from the plurality of analog radio frequency input ports to respective inbound digital stream representations thereof;
a digital baseband processor configured to concurrently process the plurality of inbound digital stream representations and the plurality of outbound digital stream representations;
a non-blocking switch matrix configured to concurrently selectively switch the plurality of outbound digital stream representations between the first converter and the digital baseband processor, and the plurality of inbound digital stream representations, without preceding signal downconversion, between the second converter and the digital baseband processor.

12. The radio system according to claim 11 , wherein the first converter is configured to convert the plurality of radio frequency signals between the first plurality of digital stream representations to the respective outbound analog representations thereof at an oversampled data rate.

13. The radio system according to claim 11 , wherein the non-blocking switch matrix comprises a first non-blocking n×m switch matrix, where n and m are each at least 4, which is configured to receive the first plurality of digitized signals which have respectively asynchronous digital clocks, and to switch the plurality of digitized signals together with their respective asynchronous digital clocks.

14. The radio system according to claim 11 , further comprising digital channelizer, configured to generate a sub-band signal component by at least one of digital mixing and digital filtering.

15. The radio system according to claim 11 , wherein the non-blocking switch matrix is configured to multicast.

16. The radio system according to claim 11 , wherein the plurality of outbound digital stream representations and the plurality of inbound digital stream representations each have a bit rate of at least in excess of 40 Gbps.

17. The radio system according to claim 11 , wherein the non-blocking switch matrix comprises single flux quantum logic.

18. The radio system according to claim 11 , wherein the non-blocking switch matrix comprises at least one non-destructive readout switch.

19. The radio system according to claim 11 , wherein the non-blocking switch matrix comprises a Banyan network.

20. The radio system according to claim 11 , wherein the plurality of inbound digital stream representations comprise at least two respective concurrent inbound digital stream representations having different respective clock rates, and the non-blocking switch matrix is configured to concurrently switch the at least two respective inbound digital stream representations having different respective clock rates.

Assignees

• Hypres Inc

Inventors

• Gupta Deepnarayan

Classifications

• H04W56/0015 Primary

  one node acting as a reference for the others · CPC title

• H04B1/005

  adapting radio receivers, transmitters andtransceivers for operation on two or more bands, i.e. frequency ranges · CPC title

• H04B1/0483

  Transmitters with multiple parallel paths · CPC title

• H04B1/40

  Circuits · CPC title