Demultiplexer and method of controlling the same, and display device

Patent metadata

Field	Value
Publication number	US-11012274-B2
Application number	US-201916414478-A
Country	US
Kind code	B2
Filing date	May 16, 2019
Priority date	May 17, 2018
Publication date	May 18, 2021
Grant date	May 18, 2021

Abstract

A demultiplexer includes a voltage boost circuit and at least one data selection output circuit. The voltage boost circuit is coupled to N second-stage selection signal input terminals and N first-stage selection signal input terminals, N is greater than or equal to 2, and N is a positive integer. Each data selection output circuit is coupled to a data input terminal, N data output terminals and the N first-stage selection signal input terminals.

First claim

What is claimed is:

1. A demultiplexer, comprising:
a voltage boost circuit, wherein the voltage boost circuit is coupled to N second-stage selection signal input terminals and N first-stage selection signal input terminals, the N second-stage selection signal input terminals are in one-to-one correspondence with the N first-stage selection signal input terminals, and the voltage boost circuit is configured to successively boost voltages input via the N second-stage selection signal input terminals and output boosted voltages to corresponding first-stage selection signal input terminals, wherein N is greater than or equal to 2, and N is a positive integer; and
at least one data selection output circuit, wherein each data selection output circuit is coupled to a data input terminal, N data output terminals and the N first-stage selection signal input terminals, and the data selection output circuit is configured to successively output data signals from the data input terminal to the N data output terminals under control of the N first-stage selection signal input terminals;
wherein the voltage boost circuit includes N voltage boost sub-circuits, each voltage boost sub-circuit is coupled to a corresponding first-stage selection signal input terminal and a corresponding second-stage selection signal input terminal, and
a (K−1)th voltage boost sub-circuit is further configured to reset a voltage on a (K−1)th first-stage selection signal input terminal when a Kth voltage boost sub-circuit boosts a voltage input via a Kth second-stage selection signal input terminal, K is greater than or equal to 2 and is less than or equal to N, and K is a positive integer; and
each voltage boost sub-circuit includes:
a coupling capacitor, wherein a first electrode of the coupling capacitor is coupled to a corresponding second-stage selection signal input terminal, a second electrode of the coupling capacitor is coupled to an auxiliary signal input terminal and a corresponding first-stage selection signal input terminal, and the coupling capacitor is configured to add a voltage input via the second-stage selection signal input terminal to a voltage input via the auxiliary signal input terminal and output an added voltage to the first-stage selection signal input terminal;
a reset module, wherein the reset module is coupled to the first-stage selection signal input terminal, a control signal input terminal and a first voltage terminal, and the reset module is configured to transmit a voltage signal input via the first voltage terminal to the first-stage selection signal input terminal under control of a voltage input via the control signal input terminal, so as to reset a voltage on the first-stage selection signal input terminal; and
an input module, wherein the input module includes a second thin film transistor, a control electrode and a first electrode of the second thin film transistor are coupled to the auxiliary signal input terminal, and a second electrode of the second thin film transistor is coupled to the second electrode of the coupling capacitor, and the input module is configured to transmit the voltage input via the auxiliary signal input terminal to the second electrode of the coupling capacitor.

2. The demultiplexer according to claim 1 , wherein the reset module includes a first thin film transistor, a control electrode of the first thin film transistor is coupled to the control signal input terminal, a first electrode of the first thin film transistor is coupled to the first-stage selection signal input terminal, and a second electrode of the first thin film transistor is coupled to the first voltage terminal.

3. The demultiplexer according to claim 1 , further comprising control signal input terminals and second-stage selection signal input terminals, wherein
a (K−1)th control signal input terminal is coupled to the Kth second-stage selection signal input terminal, wherein the (K−1)th control signal input terminal is a control signal input terminal coupled to a reset module in the (K−1)th voltage boost sub-circuit, and the Kth second-stage selection signal input terminal is a second-stage selection signal input terminal coupled to a coupling capacitor in the Kth voltage boost sub-circuit; and
an Nth control signal input terminal is coupled to a first second-stage selection signal input terminal, wherein the Nth control signal input terminal is a control signal input terminal coupled to a reset module in an Nth voltage boost sub-circuit, and the first second-stage selection signal input terminal is a second-stage selection signal input terminal coupled to a coupling capacitor in a first voltage boost sub-circuit.

4. The demultiplexer according to claim 3 , wherein each voltage boost sub-circuit further includes an input module coupled to the auxiliary signal input terminal and the coupling capacitor;
the demultiplxer further comprises auxiliary signal input terminals;
a (K−1)th second-stage selection signal input terminal is coupled to a Kth auxiliary signal input terminal, wherein the (K−1)th second-stage selection signal input terminal is a second-stage selection signal input terminal coupled to a coupling capacitor in the (K−1)th voltage boost sub-circuit, and the Kth auxiliary signal input terminal is an auxiliary signal input terminal coupled to an input module in the Kth voltage boost sub-circuit; and
an Nth second-stage selection signal input terminal is coupled to a first auxiliary signal input terminal, wherein the Nth second-stage selection signal input terminal is a second-stage selection signal input terminal coupled to a coupling capacitor in the Nth voltage boost sub-circuit, and the first auxiliary signal input terminal is an auxiliary signal input terminal coupled to an input module in the first voltage boost sub-circuit.

5. The demultiplexer according to claim 1 , wherein each data selection output circuit includes N control switches electrically connected to the data input terminal, wherein each control switch is coupled to a first-stage selection signal input terminal and a data output terminal; and
each control switch is configured to transmit a data signal from the data input terminal to the data output terminal coupled thereto under control of the first-stage selection signal input terminal coupled thereto.

6. The demultiplexer according to claim 5 , wherein each control switch includes a third thin film transistor, a control electrode of the third thin film transistor is coupled to a corresponding first-stage selection signal input terminal, a first electrode of the third thin film transistor is coupled to the data input terminal, and a second electrode of the third thin film transistor is coupled to the data output terminal.

7. The demultiplexer according to claim 6 , wherein the third thin film transistor is an N-type thin film transistor.

8. A display device, comprising:
a plurality of data lines; and
the demultiplexer according to claim 1 , wherein a data output terminal coupled to the demultiplexer is coupled to a data line.

9. The display device according to claim 8 , further comprising a plurality of pixels, wherein each pixel includes N sub-pixels; and
each pixel corresponds to a data selection output circuit of the demultiplexer, and the N sub-pixels in each pixel are coupled to a corresponding data selection output circuit through N data lines coupled one-to-one to data output terminals.

10. A method of controlling the demultiplexer according to claim 1 , the method comprising:
in a pre-charge period, inputting a first voltage signal to the auxiliary signal input terminal coupled to the voltage boost sub-circuit, so as to write the first voltage signal to the coupling capacitor in

Assignees

• Boe Technology Group Co Ltd

Inventors

• Yuan Lijun
• Zheng Haoliang
• Shang Guangliang
• Yao Xing
• Han Mingfu

Classifications

• H03D1/2227 Primary

  using switches for the decoding (diodes used as switches H03D1/2218) · CPC title

• H03D1/2209

  Decoders for simultaneous demodulation and decoding of signals composed of a sum-signal and a suppressed carrier, amplitude modulated by a difference signal, e.g. stereocoders · CPC title

• H04L27/2601 Primary

  Multicarrier modulation systems · CPC title

• G09G3/2092

  Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165) · CPC title