Line driver circuit

Patent metadata

Field	Value
Publication number	US-11012264-B2
Application number	US-201916701717-A
Country	US
Kind code	B2
Filing date	Dec 3, 2019
Priority date	Feb 20, 2019
Publication date	May 18, 2021
Grant date	May 18, 2021

Abstract

A line driver circuit includes a first input terminal, a second input terminal, a first input stage, a second input stage, a first output stage, and a second output stage. The first input stage includes a first input coupled to the first input terminal, and a second input coupled to the second input terminal. The second input stage includes a first input coupled to the first input terminal, and a second input coupled to the second input terminal. The first output stage includes a first input coupled to a first output terminal of the first input stage and a second input coupled to a first output terminal of the first input stage. A second output stage includes a first input coupled to a second output terminal of the first input stage and a second input coupled to a second output terminal of the first input stage.

First claim

What is claimed is:

1. A line driver circuit, comprising:
a first input terminal;
a second input terminal;
a first input stage comprising:
a first input coupled to the first input terminal; and
a second input coupled to the second input terminal;

a second input stage comprising:
a first input coupled to the first input terminal; and
a second input coupled to the second input terminal;

a first output stage comprising:
a first input coupled to a first output terminal of the first input stage;
a second input coupled to a first output terminal of the second input stage; and
a first output; and

a second output stage comprising:
a first input coupled to a second output terminal of the first input stage;
a second input coupled to a second output terminal of the second input stage; and

a second output;
wherein the first input stage comprises:
a current source;
a first transistor comprising:
a first terminal coupled to the first input of the first input stage; and
a second terminal coupled to the current source;

a second transistor comprising:
a first terminal coupled to the second input of the first input stage; and
a second terminal coupled to the current source;

a third transistor comprising:
a first terminal coupled to a third terminal of the first transistor; and
a second terminal coupled to a common voltage source;

a fourth transistor comprising:
a first terminal coupled to a third terminal of the second transistor; and
a second terminal coupled to the common voltage source;

a first amplifier circuit comprising:
a first input terminal coupled to the first terminal of the third transistor and the first terminal of the fourth transistor; and
an output terminal coupled to a third terminal of the third transistor and a third terminal of the fourth transistor.

2. The line driver circuit of claim 1 , wherein:
the current source is a first current source; and
the first input stage comprises:
a reference circuit comprising:
a second current source;
a fifth transistor comprising:
a first terminal and a second terminal coupled to the second current source and a third terminal of the first amplifier circuit; and
a third terminal coupled to the common voltage source.

3. The line driver circuit of claim 1 , wherein:
the current source is a first current source; and
the second input stage comprises:
a second current source;
a fifth transistor comprising:
a first terminal coupled to the first input of the second input stage; and
a second terminal coupled to the second current source;

a sixth transistor comprising:
a first terminal coupled to the second input of the second input stage; and
a second terminal coupled to the second current source;

a seventh transistor comprising:
a first terminal coupled to a third terminal of the fifth transistor; and
a second terminal coupled to a power supply rail;

an eighth transistor comprising:
a first terminal coupled to a third terminal of the sixth transistor; and
a second terminal coupled to the power supply rail;

a second amplifier circuit comprising:
a first input terminal coupled to the first terminal of the seventh transistor and the first terminal of the eighth transistor; and
an output terminal coupled to a third terminal of the seventh transistor and a third terminal of the eighth transistor.

4. The line driver circuit of claim 3 , wherein the first input stage comprises:
a reference circuit comprising:
a third current source;
a ninth transistor comprising:
a first terminal and a second terminal coupled to the third current source and a third terminal of the second amplifier circuit; and
a third terminal coupled to the power supply rail.

5. The line driver circuit of claim 3 , wherein the first output stage comprises:
a ninth transistor comprising:
a first terminal coupled to the first input of the first output stage; and
a second terminal coupled to a power supply rail; and

a tenth transistor comprising:
a first terminal coupled to the second input of the first output stage;
a second terminal coupled to a third terminal of the first transistor of the first output stage; and
a third terminal coupled to a common voltage source.

6. The line driver circuit of claim 5 , wherein the second output stage comprises:
an eleventh transistor comprising:
a first terminal coupled to the first input of the second output stage; and
a second terminal coupled to the power supply rail;

a twelfth transistor comprising:
a first terminal coupled to the second input of the second output stage;
a second terminal coupled to a third terminal of the eleventh transistor; and
a third terminal coupled to the common voltage source.

7. The line driver circuit of claim 6 , further comprising:
a first output terminal;
a second output terminal;
a first resistor comprising:
a first terminal coupled to the first output of the first output stage; and
a second terminal coupled to the first output terminal;

a second resistor comprising:
a first terminal coupled to the second output of the second output stage; and
a second terminal coupled to the second output terminal;

a third resistor comprising a first terminal coupled to the first output terminal;
a fourth resistor comprising:
a first terminal coupled to the second output terminal; and
a second terminal coupled to a second terminal of the third resistor; and

a capacitor comprising:
a first terminal coupled to the second terminal of the fourth resistor; and
a second terminal coupled to the common voltage source.

8. A line driver circuit, comprising:
a first differential input stage configured to receive a differential input signal;
a second differential input stage configured to receive the differential input signal;
a first output stage coupled to the first differential input stage and the second differential input stage, and configured to generate a positive signal portion of a differential output signal based on a first signal generated by the first differential input stage and a second signal generated by the second differential input stage; and
a second output stage coupled to the first differential input stage and the second differential input stage, and configured to generate a negative signal portion of the differential output signal based on a third signal generated by the first differential input stage and a fourth signal generated by the second differential input stage;
wherein the first differential input stage comprises:
a first input transistor;
a second input transistor coupled to the first input transistor;
a first drive transistor coupled to the first input transistor;
a second drive transistor coupled to the second input transistor; and
an amplifier circuit configured to control the first drive transistor and the second drive transistor based on a common mode output voltage of the first differential input stage.

9. The line driver circuit of claim 8 , wherein the first differential input stage comprises a reference circuit coupled to the amplifier circuit.

10. A line driver circuit, comprising:
a first differential input stage configured to receive a differential input signal;
a second differential input stage configured to receive the differential input signal;
a first output stage coupled to the first differential input stage and the second differential input stage, and configured to generate a positive signal portion of a differential output signal based on a first signal generated by the first differential input stage and a second signal generated by the second differential input stage; and
a second output stage coupled to the first diffe

Assignees

• Texas Instruments Inc

Inventors

• Kattamuri Rama Santosh Neelim Kumar
• Seth Sumantra
• Sharma Vikram

Classifications

• H03F3/45183

  Long tailed pairs (H03F3/4521, H03F3/45237 take precedence) · CPC title

• H04L25/4919

  using balanced multilevel codes (H04L25/4927 takes precedence) · CPC title

• H03F2203/45418

  the CMCL comprising a resistor addition circuit · CPC title

• H03F3/45071

  with semiconductor devices only · CPC title

• H03F3/211

  using a combination of several amplifiers (H03F3/60 takes precedence) · CPC title