Control device of motor, control system, and control method

Patent metadata

Field	Value
Publication number	US-11012013-B2
Application number	US-201916353246-A
Country	US
Kind code	B2
Filing date	Mar 14, 2019
Priority date	Sep 18, 2018
Publication date	May 18, 2021
Grant date	May 18, 2021

Abstract

According to one embodiment, there is provided a control device including a drive circuit and a control circuit. The drive circuit includes a plurality of transistors and a current determination circuit. The plurality of transistors is electrically connected in parallel to each other between a first node and a second node. The first node is connected to a power supply circuit. The second node is connected to a DC motor. The current determination circuit determines a current flowing between the first node and the second node. The control circuit generates a control signal to control a number of transistors to be turned on among the plurality of transistors in accordance with the determined current. The drive circuit drives the DC motor using a current in response to the control signal.

First claim

What is claimed is:

1. A control device comprising:
a drive circuit including a plurality of transistors and a current determination circuit, the plurality of transistors being electrically connected in parallel to each other between a first node and a second node, the first node being connected to a power supply circuit, the second node being connected to a DC motor, the current determination circuit determining a total current flowing between the first node and the second node; and
a control circuit that generates a control signal to control a number of transistors to be turned on among the plurality of transistors in accordance with the determined total current,
wherein the drive circuit drives the DC motor using a current in response to the control signal, and
the control circuit
turns on a first number of transistors among the plurality of transistors in a first period,
turns on a second number of transistors, smaller than the first number, among the plurality of transistors in a second period, and
turns on a third number of transistors, smaller than the second number, among the plurality of transistors in a third period.

2. The control device according to claim 1 , wherein
the plurality of transistors includes a first transistor and a second transistor, and
the control circuit turns on the first transistor at a first timing and turns on the second transistor at a second timing after the first timing in the first period.

3. The control device according to claim 2 , wherein
the plurality of transistors further includes a third transistor, and
the control circuit turns on the third transistor at a third timing after the second timing in the first period.

4. The control device according to claim 1 , wherein
the current determination circuit determines whether a total current flowing between the first node and the second node exceeds a target total current, and outputs a determination result to the control circuit.

5. The control device according to claim 4 , wherein
the control circuit controls the target total current in accordance with a control waveform pattern.

6. The control device according to claim 1 , wherein
the first period is a period during which a target total current between the first node and the second node is controlled to a first current value, and
the second period is a period during which the target total current between the first node and the second node is controlled to a second current value having a smaller absolute value than the first current value.

7. The control device according to claim 1 , wherein
the first period is a period during which a target total current between the first node and the second node is controlled to a first current value,
the second period is a period during which the target current between the first node and the second node is controlled to a second current value having a smaller absolute value than the first current value, and
the third period is a period during which the target total current between the first node and the second node is controlled to a third current value having a smaller absolute value than the second current value.

8. The control device according to claim 1 , wherein
the second period is a period before the first period,
the plurality of transistors includes a first transistor and a second transistor, and
the control circuit turns on the first transistor in the second period and turns on the first transistor and the second transistor in the first period.

9. The control device according to claim 1 , wherein the second period is a period before the first period, the third period is a period before the second period, the plurality of transistors includes a first transistor, a second transistor, and a third transistor, and the control circuit turns on the first transistor in the third period, turns on the first transistor and the second transistor in the second period, and turns on the first transistor, the second transistor, and the third transistor in the third period.

10. The control device according to claim 1 , wherein
the second period is a period after the first period,
the plurality of transistors includes a first transistor and a second transistor, and
the control circuit turns on the first transistor and the second transistor in the first period and turns on the first transistor in the second period.

11. The control device according to claim 1 , wherein
the second period is a period after the first period,
the third period is a period after the second period,
the plurality of transistors includes a first transistor, a second transistor, and a third transistor, and
the control circuit turns on the first transistor, the second transistor, and the third transistor in the first period, turns on the first transistor and the second transistor in the second period, and turns on the first transistor in the third period.

12. The control device according to claim 2 , wherein
the control circuit turns on the first transistor and the second transistor at an identical timing in the second period.

13. The control device according to claim 3 , wherein
the control circuit turns on the first transistor, the second transistor, and the third transistor at an identical timing in the second period.

14. The control device according to claim 1 , wherein
the plurality of transistors is disposed to be divided into a plurality of regions in a mounting region, and
a configuration corresponding to the current determination circuit is disposed to be divided among the plurality of regions.

15. The control device according to claim 1 , wherein
the current determination circuit comprises:
a replica transistor having a dimension corresponding to each of the plurality of transistors;
a reference current source electrically connected to the replica transistor via a third node; and
a determination circuit that compares a voltage of the first node with a voltage of the third node and outputs a comparison result as the determination result to the control circuit.

16. The control device according to claim 15 , wherein
the control circuit generates a current in accordance with a target total current in the reference current source.

17. A control system comprising:
a power supply circuit; and
the control device according to claim 1 disposed between the power supply circuit and a DC motor.

18. A control method comprising:
determining a total current flowing between a first node and a second node, the first node being connected to a power supply circuit, the second node being connected to a DC motor, a plurality of transistors being electrically connected in parallel between the first node and the second node;
generating a control signal to control a number of transistors to be turned on among the plurality of transistors in accordance with the determined total current; and
driving a DC motor with a current corresponding to the control signal, wherein
the driving includes
turning on a first number of transistors among the plurality of transistors in a first period,
turning on a second number of transistors, smaller than the first number, among the plurality of transistors in a second period, and
turning on a third number of transistors, smaller than the second number, among the plurality of transistors in a third period.

Assignees

• Toshiba Kk
• Toshiba Electronic Devices & Storage Corp

Inventors

• Kimura Hideki

Classifications

• H02P8/22 Primary

  Control of step size; Intermediate stepping, e.g. microstepping · CPC title

• H02K11/33

  Drive circuits, e.g. power electronics (H02K11/38 takes precedence) · CPC title

• H02P7/28 Primary

  using semiconductor devices · CPC title

• H02P6/28 Primary

  Arrangements for controlling current (H02P6/10 takes precedence) · CPC title

• H02P8/12

  Control or stabilisation of current · CPC title