Thin film transistor and manufacturing method thereof, array substrate and display device

Patent metadata

Field	Value
Publication number	US-11011645-B2
Application number	US-201916446744-A
Country	US
Kind code	B2
Filing date	Jun 20, 2019
Priority date	Jul 6, 2018
Publication date	May 18, 2021
Grant date	May 18, 2021

Abstract

The present disclosure discloses a thin film transistor and a manufacturing method thereof, an array substrate and a display device, and belongs to the field of semiconductor display technology. The active layer of the thin film transistor is made of a CIGS material. By manufacturing the active layer of the thin film transistor with the CIGS material, and the crystal defects of the CIGS are less than LTPS and IGZO, the mobility of the thin film transistor is higher, and the switching speed of the thin film transistor is faster, thereby being advantageous to further improve the resolution of the display device.

First claim

What is claimed is:

1. A thin film transistor, wherein an active layer of the thin film transistor is made of a Cu—In—Ga—Se (CIGS) material; and
wherein the active layer of the thin film transistor comprises a source electrode contact region in contact with a source electrode, a drain electrode contact region in contact with a drain electrode, and an active region connecting the source electrode contact region and the drain electrode contact region; a selenium content of the source electrode contact region and a selenium content of the drain electrode contact region are less than a selenium content of the active region; and a copper content of the source electrode contact region, the drain electrode contact region and the active region are all equal.

2. The thin film transistor according to claim 1 , wherein the active layer of the thin film transistor comprises a source electrode contact region in contact with a source electrode, a drain electrode contact region in contact with a drain electrode, and an active region connecting the source electrode contact region and the drain electrode contact region; and a copper content and a selenium content of the source electrode contact region, the drain electrode contact region and the active region are all equal.

3. The thin film transistor according to claim 1 , wherein the active layer of the thin film transistor comprises a source electrode contact region in contact with a source electrode, a drain electrode contact region in contact with a drain electrode, and an active region connecting the source electrode contact region and the drain electrode contact region; a copper content of the source electrode contact region and a copper content of the drain electrode contact region are greater than a copper content of the active region; and a selenium content of the source electrode contact region, the drain electrode contact region and the active region are all equal.

4. The thin film transistor according to claim 3 , wherein both the source electrode and the drain electrode contain copper.

5. The thin film transistor according to claim 4 , wherein both the source electrode and the drain electrode are made of one of the following materials: copper, a copper alloy, and a copper-based composite material.

6. The thin film transistor according to claim 1 , wherein a gate electrode of the thin film transistor is made of one of the following materials: copper, aluminum, titanium, molybdenum or a molybdenum-based composite material.

7. A manufacturing method for a thin film transistor, comprising:
forming a CIGS film layer on a substrate; and
patterning the CIGS film layer to obtain an active layer; and
wherein the active layer comprises a source electrode contact region, a drain electrode contact region, and an active region connecting the source electrode contact region and the drain electrode contact region; and
the manufacturing method further comprises:
forming a source electrode and a drain electrode on the active layer, part of the region of the source electrode covering on the source electrode contact region, and part of the region of the drain electrode covering on the drain electrode contact region; and
selenizing the active region; and
wherein a selenium content of the source electrode contact region and a selenium content of the drain electrode contact region are less than a selenium content of the active region; and a copper content of the source electrode contact region, the drain electrode contact region and the active region are all equal.

8. The manufacturing method according to claim 7 , wherein the active layer comprises a source electrode contact region, a drain electrode contact region, and an active region connecting the source electrode contact region and the drain electrode contact region; and
the manufacturing method further comprises:
forming a source electrode and a drain electrode on the active layer, the source electrode and the drain electrode containing copper, part of the region of the source electrode covering on the source electrode contact region, and part of the region of the drain electrode covering on the drain electrode contact region; and
annealing the substrate on which the source electrode and the drain electrode are formed, so that the copper in the source electrode diffuses to the source electrode contact region and the copper in the drain electrode diffuses to the drain electrode contact region.

9. The manufacturing method according to claim 8 , wherein the annealing temperature of the annealing treatment is 400° C. to 600° C.

10. The manufacturing method according to claim 8 , wherein the manufacturing method further comprises:
selenizing the active layer before the source electrode and the drain electrode are formed on the active layer.

11. An array substrate, comprising a thin film transistor, wherein an active layer of the thin film transistor is made of a CIGS material; and
wherein the active layer of the thin film transistor comprises a source electrode contact region in contact with a source electrode, a drain electrode contact region in contact with a drain electrode, and an active region connecting the source electrode contact region and the drain electrode contact region; a selenium content of the source electrode contact region and a selenium content of the drain electrode contact region are less than a selenium content of the active region; and a copper content of the source electrode contact region, the drain electrode contact region and the active region are all equal.

12. The array substrate according to claim 11 , wherein the active layer of the thin film transistor comprises a source electrode contact region in contact with a source electrode, a drain electrode contact region in contact with a drain electrode, and an active region connecting the source electrode contact region and the drain electrode contact region; and a copper content and a selenium content of the source electrode contact region, the drain electrode contact region and the active region are all equal.

13. The array substrate according to claim 11 , wherein the active layer of the thin film transistor comprises a source electrode contact region in contact with a source electrode, a drain electrode contact region in contact with a drain electrode, and an active region connecting the source electrode contact region and the drain electrode contact region; a copper content of the source electrode contact region and a copper content of the drain electrode contact region are greater than a copper content of the active region; and a selenium content of the source electrode contact region, the drain electrode contact region and the active region are all equal.

14. The array substrate according to claim 13 , wherein both the source electrode and the drain electrode of the thin film transistor contain copper.

15. The array substrate according to claim 14 , wherein both the source electrode and the drain electrode are made of one of the following materials: copper, a copper alloy, and a copper-based composite material.

16. The array substrate according to claim 11 , wherein a gate electrode of the thin film transistor is made of one of the following materials: copper, aluminum, titanium, molybdenum or a molybdenum-based composite material.

17. A display device, comprising the array substrate according to claim 11 .

Assignees

• Boe Technology Group Co Ltd

Inventors

• Ren Qingrong
• Yuan Guangcai
• Guan Feng
• Li Dongsheng
• Sun Jianming

Classifications

• H10D30/0312

  characterised by the gate electrodes · CPC title

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10D62/80

  characterised by the materials · CPC title

• H10D30/6713

  characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes · CPC title

• H10D64/62

  Electrodes ohmically coupled to a semiconductor · CPC title