Array substrate for reducing coupling effect, display panel, display device, operating method, and manufacturing method

Patent metadata

Field	Value
Publication number	US-11011091-B2
Application number	US-201916530214-A
Country	US
Kind code	B2
Filing date	Aug 2, 2019
Priority date	Jan 2, 2019
Publication date	May 18, 2021
Grant date	May 18, 2021

Abstract

An array substrate, a display panel, a display device, an operating method, and a manufacturing method are disclosed. The array substrate includes a wiring structure formed on a base substrate, and the wiring structure includes a common electrode line for connecting a common electrode, and a plurality of signal lines. The plurality of signal lines include at least one pair of signal lines, and the pair of signal lines include a first signal line and a second signal line. The first signal line is disposed on a first side of the common electrode line and is configured to transmit a driving signal for a gate driving circuit. The second signal line is disposed on a second side of the common electrode line and is configured to transmit an inverted signal of the driving signal.

First claim

What is claimed is:

1. A display panel, comprising:
an array substrate comprising:
a wiring structure formed on a base substrate, the wiring structure comprising:
a common electrode line, and
a plurality of signal lines, wherein the common electrode line is for connecting to a common electrode,
wherein the plurality of signal lines comprises a pair of signal lines, and wherein the pair of signal lines comprises a first signal line, and a second signal line,
wherein the first signal line is disposed on a first side of the common electrode line and is configured to transmit a driving signal for a gate driving circuit, and wherein the second signal line is disposed on a second side of the common electrode line and is configured to transmit an inverted signal of the driving signal, and wherein the second signal line is connected to an impedance load;

wherein the driving signal comprises at least one clock signal for the gate driving circuit, wherein the first signal line of the pair of signal lines is a clock signal line for transmitting the clock signal, wherein the first signal line is closest to the common electrode line, and wherein the second signal line is configured to transmit an inverted signal of the clock signal; and
wherein a vertical distance between the first signal line and the common electrode line is a first distance, wherein a vertical distance between the second signal line and the common electrode line is a second distance, and wherein the first distance is equal to the second distance.

2. The display panel according to claim 1 , wherein the impedance load is a dummy gate driving unit of the gate driving circuit.

3. The display panel according to claim 1 , wherein the first signal line is connected to the gate driving circuit, and the gate driving circuit is integrated on the base substrate.

4. The display panel according to claim 1 , wherein the first side is a side of the common electrode line close to the gate driving circuit, and the second side is a side of the common electrode line away from the gate driving circuit.

Assignees

• Beijing Boe Display Tech Co
• Boe Technology Group Co Ltd

Inventors

• Zhang Qiang
• Dong Dianzheng
• Wang Guangxing
• Chen Pengming
• Xu Wenpeng
• Lin Wan
• Wang Haixu
• Wang Leiyang

Classifications

• H10D86/441 Primary

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D86/021

  of multiple TFTs · CPC title

• G09G3/3655

  Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors · CPC title

• G09G2320/0219

  Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling · CPC title