Data storage device and operating method thereof

Patent metadata

Field	Value
Publication number	US-11010289-B2
Application number	US-201916289096-A
Country	US
Kind code	B2
Filing date	Feb 28, 2019
Priority date	Oct 7, 2014
Publication date	May 18, 2021
Grant date	May 18, 2021

Abstract

A data storage device includes a nonvolatile memory apparatus suitable for accessing a target region corresponding to an access command, and a processor suitable for calculating a first hash value corresponding to the target region based on a first hash function, and updating an access count that is indexed by the first hash value.

First claim

What is claimed is:

1. A data storage device comprising:
a nonvolatile memory apparatus configured to access a target region corresponding to a read command; and
a processor configured to increase a first access count and a second access count after the accessing of the target region, the first access count corresponding to a plurality of first regions including the target region, the second access count corresponding to a plurality of second regions including the target region, and perform a data inspection operation on a region related to the target region when any one of the access counts reaches a threshold,
wherein the processor decreases an access count which reaches the threshold to a predetermined value other than zero after performing the data inspection operation.

2. The data storage device of claim 1 , wherein the processor calculates one or more hash values corresponding to the target region based on an address of the target region, and increases the access counts that are indexed by the hash values.

3. The data storage device of claim 1 , wherein the first regions and the second regions correspond to different word lines.

4. The data storage device of claim 1 , wherein the processor compares the access counts with the threshold, and performs the data inspection operation for one or more neighboring regions that are adjacent to the target region according to the comparison.

5. A data storage device comprising:
a nonvolatile memory apparatus including a plurality of first regions corresponding to a first hash value and a plurality of second regions corresponding to a second hash value; and
a processor configured to manage a first common access count corresponding to the plurality of first regions and a second common access count corresponding to the plurality of second regions,
wherein the first common access count is indexed by the first hash value and the second common access count is indexed by the second hash value,
wherein the first regions and the second regions include a target region commonly, and
wherein the processor performs a data inspection operation for one or more neighboring regions adjacent to the target region when any one of the first common access count and the second common access count reaches a threshold, and decreases the any one of the first common access count and the second common access count which reaches the threshold to a predetermined value other than zero after performing the data inspection operation.

6. The data storage device of claim 5 , wherein the plurality of first regions and the plurality of second regions correspond to different word lines.

7. The data storage device of claim 5 , wherein the process comprises a first hashing unit configured to calculate the first hash value based on an address of one of the plurality of first regions and a second hashing unit configured to calculate the second hash value based on an address of one of the plurality of second regions.

8. The data storage device of claim 5 , wherein the processor increases the first common access count and the second common access count when accessing the target region.

9. A method for operating a data storage device, comprising:
in response to a read command, accessing a target region included in a nonvolatile memory apparatus;
increasing a first access count and a second access count after the accessing of the target region, the first access count corresponding to a plurality of first regions including the target region, the second access count corresponding to a plurality of second regions including the target region;
performing a data inspection operation on a region related to the target region when any one of the access counts reaches a threshold; and
decreasing an access count which reaches the threshold to a predetermined value other than zero after performing the data inspection operation,
wherein the first regions include one or more regions which are not included in the second regions, and the second regions include one or more regions which are not included in the first regions.

10. The method of claim 9 , wherein the first regions and the second regions correspond to different word lines.

11. The method of claim 9 , wherein the increasing of the access counts further comprises:
calculating one or more hash values corresponding to the target region based on an address of the target region; and
increasing the access counts that are indexed by the hash values.

12. The method of claim 9 , wherein the performing of the data inspection operation comprises:
comparing the access counts with the threshold; and
performing the data inspection operation for one or more neighboring regions that are adjacent to the target region according to the comparison.

13. The method of claim 12 , wherein the performing of the data inspection operation for the neighboring region comprises:
reading data stored in the neighboring regions;
checking an error occurrence rate of the data read from the neighboring regions; and
performing selectively a reclaim operation for recovering the data stored in the neighboring regions according to the error occurrence rate.

Assignees

• Sk Hynix Inc

Inventors

• Kim Se Hyun
• Yang Joong Seob
• Kim Eui Jin
• Lee Jong Min

Classifications

• G06F2212/7204

  Capacity control, e.g. partitioning, end-of-life degradation · CPC title

• G06F12/0238 Primary

  Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory · CPC title

• G11C16/3495

  Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically · CPC title

• G06F2212/7205

  Cleaning, compaction, garbage collection, erase control · CPC title

• G06F2212/1032

  Reliability improvement, data loss prevention, degraded operation etc · CPC title