High performance logical device

Patent metadata

Field	Value
Publication number	US-11010060-B2
Application number	US-201916446679-A
Country	US
Kind code	B2
Filing date	Jun 20, 2019
Priority date	Apr 27, 2017
Publication date	May 18, 2021
Grant date	May 18, 2021

Abstract

A high performance logical device having low latency may be provided. I/Os to the logical device may be sent only to a primary director having sole ownership of the logical device. The primary director may perform operations locally for the logical device. Such operations may include allocating global memory for use with the logical device from only a global memory portion that is local to the primary director. The global memory may be a distributed global memory including memory from multiple directors and possibly multiple engines. Cached data for the logical device may be mirrored automatically by the data storage system. Alternatively, the cached data for the logical device may be mirrored using a host-based mirroring technique.

First claim

What is claimed is:

1. A method of processing an I/O operation comprising:
receiving, on a host, the I/O operation directed to a target location of a logical device having storage provisioned on a data storage system, wherein the data storage system includes a plurality of directors;
determining, by the host, that the logical device is configured as a high performance logical device; and
responsive to the host determining that the logical device is configured as a high performance logical device, performing I/O path optimization processing by the host in connection with sending the I/O operation to the data storage system, said I/O path optimization processing performed by the host comprising:
determining, by the host, a first director of the plurality of directors of the data storage system, wherein the first director is designated as a primary director for the logical device and wherein the primary director locally accesses a first cache location of a cache of the data storage system, wherein the first cache location is used to store cache data for the target location of the logical device, and wherein said determining the first director by the host further includes:
using, by the host, a cache slot allocation algorithm that maps the target location of the logical device to the first director that is predicted to locally access the first cache location used to store cache data for the target location of the logical device, wherein the cache slot allocation algorithm is also used on the data storage system by each of the plurality of directors to determine particular cache locations used to cache data for different logical addresses for a plurality of logical devices including the logical device; and

sending the I/O operation from the host to the data storage system over a path, said path being a connection from the host to the first director of the data storage system.

2. The method of claim 1 , wherein the target location denotes a logical address or location on the logical device.

3. The method of claim 1 , wherein the primary director is a specified one of the plurality of directors of the data storage system that exclusively processes I/O operations directed to the logical device.

4. The method of claim 3 , wherein the first cache location is included in a first global memory portion that is local with respect to the first director.

5. The method of claim 4 , wherein the data storage system includes a distributed global memory comprising a plurality of global memory portions including the first global memory portion, each of the plurality of directors locally accessing a different one of the plurality of global memory portions, and wherein the cache of the data storage system comprises groups of multiple cache locations, each of the groups of multiple cache locations being included in a different one of the global memory portions.

6. The method of claim 5 , wherein memory chunks allocated from global memory for use with the logical device are only allocated from the first global portion of the distributed global memory.

7. The method of claim 6 , wherein the primary director is the only one of the plurality of directors that accesses the memory chunks and the controls used in connection with shared or concurrent access to the memory chunks are disabled.

8. The method of claim 6 , wherein the primary director is included in a first engine and a second director is also included in the first engine, wherein the plurality of global memory portions of the distributed global memory includes a second global memory portion that is local with respect to the second director, and wherein the data storage system automatically performs processing to mirror first cached write data of the logical device in the first global memory portion and the second global memory portion, wherein the processing includes copying the first cached write data over a first connection used for transferring data between directors and global memory portions of the distributed global memory of the first engine.

9. The method of claim 8 , wherein the data storage system include a plurality of engines including the first engine, and a second logical device is not configured as a high performance logical device, wherein the data storage system automatically performs second processing to mirror second cached write data of the second logical device on two different cache locations of two different engines of the plurality of engines, the second processing including copying the second cached write data over a communications fabric connected to each of the plurality of directors and each of the plurality of global memory portions of the distributed global memory.

10. The method of claim 6 , wherein the primary director is included in a first engine and a second director is also included in the first engine, wherein the plurality of global memory portions of the distributed global memory includes a second global memory portion that is local with respect to the second director, and wherein host-based processing is performed to mirror first cached write data of the logical device in the first global memory portion and the second global memory portion.

11. The method of claim 1 , wherein the data storage system includes the plurality of directors on a plurality of engines, each of the plurality of engines including at least two of the plurality of directors, wherein a first of the engines includes the first director and a second director, and wherein each of the plurality of directors is configured to communicate over a fabric to access a distributed global memory of a plurality of global memory portions, each of the plurality of global memory portions being local to a different one of the plurality of directors.

12. The method of claim 11 , wherein each of the plurality of engines includes an engine-local connection used for communication between any of the plurality of directors on said each engine, wherein a first of the plurality of global memory portions is local to the first director and a second of the plurality of global memory portions is local to the second director, and wherein the logical device is configured as a high performance logical device, the data storage system automatically mirroring cached write data of the logical device in the first global memory portion and the second global memory portion, said mirroring including transferring the cached write data of the logical device, as stored in the first global memory portion, over the engine-local connection of the first engine, to the second global memory portion.

13. The method of claim 1 , wherein the I/O operation is a write operation that writes first data, wherein the first cache location is included in a first memory that is local to the primary director, wherein the plurality of directors communicate over a communications fabric, and the method comprises:
duplicating the first data in a second cache location of a second memory, wherein said duplicating includes copying the first data from the first cache location to the second cache location using a first connection rather than the communications fabric, wherein the first connection provides faster data transfer than the communications fabric and wherein the first connection is used to duplicate cached data for logical devices configured as high performance logical devices and wherein the communications fabric is used to duplicate cached data for logical devices not configured as high performance logical devices.

14. The method of claim 1 , wherein the host disables the I/O path optimization processing for I/O operations larger than a maximum threshold size.

Assignees

• Emc Ip Holding Co Llc

Inventors

• Lecrone Douglas E
• Scharland Michael J
• Mcclure Steven T
• Cartmell Jerome

Classifications

• G06F12/0895 Primary

  of parts of caches, e.g. directory or tag array · CPC title

• G06F3/0611 Primary

  in relation to response time · CPC title

• G06F3/065

  Replication mechanisms · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/067

  Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS] · CPC title