Phase detector for phase-locked loops

Patent metadata

Field	Value
Publication number	US-11005482-B1
Application number	US-202016740103-A
Country	US
Kind code	B1
Filing date	Jan 10, 2020
Priority date	Jan 10, 2020
Publication date	May 11, 2021
Grant date	May 11, 2021

Abstract

Techniques are disclosed for phase detection in a phase-locked loop (PLL) control system, such as a millimeter-wave PLL. A PLL control system includes a voltage-controlled oscillator (VCO) circuit and a sub-sampling phase detector (SSPD). The VCO circuit is configured to generate an oscillating VCO output voltage based at least in part on an error signal generated by the SSPD. The error signal is proportional to a phase difference between an oscillating reference input voltage and the oscillating VCO output voltage. The SSPD includes a switched emitter-follower (SEF) sampling network, also referred to in this disclosure as an SEF circuit. In contrast to existing CMOS-based techniques, the SEF sampling network allows the SSPD to operate up to higher frequencies, for example, greater than 100 GHz, than possible using a CMOS sampler, and is also compatible with BiCMOS processes, which generally do not have access to advanced small-geometry CMOS.

First claim

What is claimed is:

1. A phase-locked loop control system comprising:
a voltage-controlled oscillator (VCO) circuit configured to generate an oscillating VCO output voltage based at least in part on an error signal that is proportional to a phase difference between an oscillating reference input voltage and the oscillating VCO output voltage;
a buffer circuit communicatively coupled with the VCO circuit, the buffer circuit configured to generate an oscillating buffered VCO output voltage that is based on and isolated from the oscillating VCO output voltage; and
a sub-sampling phase detector communicatively coupled with the buffer circuit, the sub-sampling phase detector including a switched emitter-follower (SEF) circuit configured to generate the error signal based on the oscillating reference input voltage and the oscillating buffered VCO output voltage.

2. The system of claim 1 , wherein the SEF circuit includes a sampling capacitor configured to be driven by a switched current source.

3. The system of claim 1 , wherein the SEF circuit is configured to operate in a track phase and/or a hold phase, wherein in the track phase, the track-and-hold circuit tracks the oscillating buffered VCO output voltage, and wherein in the hold phase, the track-and-hold circuit samples and holds the buffered VCO output voltage at a steady state.

4. The system of claim 3 , wherein in the track phase, a bias current is configured to flow through the SEF circuit, causing an output of the SEF circuit to track the oscillating buffered VCO output voltage.

5. The system of claim 3 , wherein in the hold phase, the switched current source is configured to be cut off from the SEF circuit, causing the oscillating buffered VCO output voltage to be sampled and held at the steady state across a sampling capacitor.

6. The system of claim 1 , further comprising a charge pump and/or an amplifier in electronic communication with the sub-sampling phase detector and the VCO circuit, the charge pump and/or the amplifier configured to receive the error signal and output a current pulse having a width approximately equal to the phase difference between the reference input and the buffered VCO output voltage.

7. The system of claim 6 , further comprising a low pass filter in electronic communication with the sub-sampling phase detector and the VCO circuit, the low pass filter configured to remove high-frequency components from the current pulse and pass low-frequency components of the current pulse to the VCO circuit.

8. A method of controlling a phase-locked loop control system, the method comprising:
generating, by a voltage-controlled oscillator (VCO) circuit, an oscillating VCO output voltage based at least in part on an error signal that is proportional to a phase difference between an oscillating reference input voltage and the oscillating VCO output voltage;
generating, by a buffer circuit in electronic communication with the VCO circuit, an oscillating buffered VCO output voltage that is based on and isolated from the oscillating VCO output voltage; and
generating, by a sub-sampling phase detector in electronic communication with the buffer circuit, the error signal based on the oscillating reference input voltage and the oscillating buffered VCO output voltage, the sub-sampling phase detector including a switched emitter-follower (SEF) circuit.

9. The method of claim 8 , wherein the SEF circuit includes a sampling capacitor, and wherein the method further comprises driving the sampling capacitor with a switched current source.

10. The method of claim 8 , wherein the SEF circuit is configured to operate in a track phase and/or a hold phase, and wherein the method further comprises, in the track phase, tracking, by the track-and-hold circuit, the oscillating buffered VCO output voltage, and in the hold phase, sampling and holding, by the track-and-hold circuit, the buffered VCO output voltage at a steady state.

11. The method of claim 10 , further comprising, in the track phase, causing an output of the SEF circuit to track the oscillating buffered VCO output voltage, wherein a bias current is configured to flow through the SEF circuit.

12. The method of claim 10 , further comprising, in the hold phase, causing the oscillating buffered VCO output voltage to be sampled and held at the steady state across a sampling capacitor, wherein the switched current source is configured to be cut off from the SEF circuit.

13. The method of claim 8 , further comprising receiving, by a charge pump and/or an amplifier in electronic communication with the sub-sampling phase detector and the VCO circuit, the error signal, and outputting, by the charge pump and/or the amplifier, a current pulse having a width approximately equal to the phase difference between the oscillating reference input voltage and the oscillating buffered VCO output voltage.

14. The method of claim 13 , further comprising causing, by a low pass filter in electronic communication with the sub-sampling phase detector and the VCO circuit, high-frequency components to be removed from the current pulse, and causing, by the low pass filter, low-frequency components of the current pulse to be passed to the VCO circuit.

15. A phase-locked loop control system comprising:
a voltage-controlled oscillator (VCO) circuit configured to generate an oscillating VCO output voltage based at least in part on an error signal that is proportional to a phase difference between an oscillating reference input voltage and the oscillating VCO output voltage;
a buffer circuit in electronic communication with the VCO circuit, the buffer circuit configured to generate an oscillating buffered VCO output voltage that is based on and isolated from the oscillating VCO output voltage, wherein the error signal is based on the oscillating reference input voltage and the oscillating buffered VCO output voltage; and
a means for generating the error signal.

16. The system of claim 15 , wherein the means for generating the error signal includes a switched emitter-follower (SEF) circuit configured to generate the error signal.

17. The system of claim 15 , wherein the means for generating the error signal is configured to operate in a track phase and/or a hold phase, wherein in the track phase, the track-and-hold circuit tracks the oscillating buffered VCO output voltage, and wherein in the hold phase, the track-and-hold circuit samples and holds the buffered VCO output voltage at a steady state.

18. The system of claim 16 , wherein the SEF circuit includes a sampling capacitor configured to be driven by a switched current source, and wherein the SEF circuit is configured to operate in a track phase and/or a hold phase, wherein in the track phase, a bias current is configured to flow through the SEF circuit, causing an output of the SEF circuit to track the oscillating buffered VCO output voltage, and wherein in the hold phase, the switched current source is configured to be cut off from the SEF circuit, causing the oscillating buffered VCO output voltage to be sampled and held at the steady state across the sampling capacitor.

19. The system of claim 15 , further comprising:
a charge pump and/or a differential pair amplifier in electronic communication with the means for generating the error signal and the VCO circuit, the charge pump and/or the differential pair amplifier configured to receive the error signal and output a current pulse having a width approximately equal to the phase difference between the reference input and the buffered VCO output voltage; and/

Assignees

• Bae Sys Inf & Elect Sys Integ

Inventors

• Stuenkel Mark E
• Hickle Mark D

Classifications

• H03L7/099

  concerning mainly the controlled oscillator of the loop · CPC title

• H03L7/093

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title

• H03L7/091 Primary

  the phase or frequency detector using a sampling device (H03L7/087 takes precedence) · CPC title

• H03L7/0992

  comprising a counter or a frequency divider · CPC title

• H03L7/0891

  the up-down pulses controlling source and sink current generators, e.g. a charge pump · CPC title