Dynamic deadtime control in a wireless transmission function

Patent metadata

Field	Value
Publication number	US-11005306-B2
Application number	US-201916368790-A
Country	US
Kind code	B2
Filing date	Mar 28, 2019
Priority date	Dec 20, 2018
Publication date	May 11, 2021
Grant date	May 11, 2021

Abstract

Embodiments described herein provide a wireless power transmitter that dynamically adjusts the deadtime to reduce power loss. Specifically, the wireless power transmitter includes a transistor circuit for switching a first voltage at a first node and a second voltage at a second node, and a LC circuit coupled between the first node and the second node. The wireless power transmitter further includes a controller coupled to the transistor circuit. The controller is configured to determine whether either of the first voltage and the second voltage is negative during a deadtime of switching. The controller is configured to increment or decrement the deadtime by an adjustment amount depending on whether negative voltage is detected.

First claim

What is claimed is:

1. A wireless power transmitter, comprising:
a transistor circuit for switching a first voltage at a first node and a second voltage at a second node;
a LC circuit coupled between the first node and the second node; and
a controller coupled to the transistor circuit, the controller configured to:
determine whether either of the first voltage and the second voltage is negative during a deadtime of switching,
increment the deadtime by an adjustment amount when none of the first voltage and the second voltage is negative during the deadtime of switching, and
decrement the deadtime by the adjustment amount when one of the first voltage and the second voltage is negative during the deadtime of switching.

2. The wireless power transmitter of claim 1 , wherein the transistor circuit receives an input voltage at a first transistor bridge and a second transistor bridge in parallel to the first transistor bridge.

3. The wireless power transmitter of claim 2 , wherein the first transistor bridge includes a first transistor switch and a second transistor switch, connected through the first node, and
the second transistor bridge includes a third transistor switch and a fourth transistor switch connected through the second node.

4. The wireless power transmitter of claim 3 , wherein the controller applies a first gate voltage to the first transistor switch and the fourth transistor switch and a reverse of the first gate voltage to the second transistor switch and the third transistor switch such that the first and the fourth transistor switches, and the second and the third transistor switches are turned on or off alternately.

5. The wireless power transmitter of claim 3 , wherein the first voltage is fed to the first transistor switch and the fourth transistor switch as a first gate voltage, and the second voltage is fed to the second transistor switch and the third transistor switch as a second gate voltage.

6. The wireless power transmitter of claim 4 , wherein the first voltage at the first node switches between a value equivalent to the input voltage and zero with a first deadtime of switching, and
the second voltage at the second node switches, reversely to the first voltage, between zero and the value equivalent to the input voltage with a second deadtime of switching.

7. The wireless power transmitter of claim 1 , wherein the deadtime is set with the incremented or decremented adjustment amount, and wherein the controller is further configured to:
operate the transistor circuit with the deadtime with the incremented or decremented adjustment amount.

8. A method for dynamically controlling a deadtime of voltage switching in a wireless power transmitter, comprising:
generating switching voltages at a first node and a second node of a transistor circuit with a deadtime;
driving, by the switching voltages, a LC circuit coupled between the first node and the second node;
determining whether either of the first voltage and the second voltage is negative during the deadtime of switching;
incrementing the deadtime by a first adjustment amount when none of the first voltage and the second voltage is negative during the deadtime of switching, and
decrementing the deadtime by a second adjustment amount when one of the first voltage and the second voltage is negative during the deadtime of switching.

9. The method of claim 8 , further comprising:
receiving an input voltage at the transistor circuit having a first transistor bridge and a second transistor bridge in parallel to the first transistor bridge,
wherein the first transistor bridge includes a first transistor switch and a second transistor switch, connected through the first node, and
the second transistor bridge includes a third transistor switch and a fourth transistor switch connected through the second node.

10. The method of claim 9 , wherein the generating switching voltages at the first node and the second node of a transistor circuit with a deadtime comprises:
turning on or off the first and the fourth transistor switches, and the second and the third transistor switches alternately by:
applying a first gate voltage to the first transistor switch and the fourth transistor switch and a reverse of the first gate voltage to the second transistor switch and the third transistor switch.

11. The method of claim 9 , further comprising:
feeding the first voltage to the first transistor switch and the fourth transistor switch as a first gate voltage; and
feeding the second voltage to the second transistor switch and the third transistor switch as a second gate voltage.

12. The method of claim 10 , further comprising:
causing the first voltage at the first node to switch between a value equivalent to the input voltage and zero with a first deadtime of switching, and
causing the second voltage at the second node to switch, reversely to the first voltage, between zero and the value equivalent to the input voltage with a second deadtime of switching.

13. The method of claim 8 , further comprising:
setting the deadtime with the incremented or decremented adjustment amount via firmware or hardware; and
operating the transistor circuit with the deadtime with the incremented or decremented adjustment amount.

14. A system for dynamically controlling a deadtime of voltage switching in a wireless power transmitter, comprising:
means for generating switching voltages at a first node and a second node of a transistor circuit with a deadtime;
means for driving, by the switching voltages, a LC circuit coupled between the first node and the second node;
means for determining whether either of the first voltage and the second voltage is negative during the deadtime of switching;
means for incrementing the deadtime by a first adjustment amount when none of the first voltage and the second voltage is negative during the deadtime of switching, and
means for decrementing the deadtime by a second adjustment amount when one of the first voltage and the second voltage is negative during the deadtime of switching.

15. The system of claim 14 , further comprising:
means for receiving an input voltage at the transistor circuit having a first transistor bridge and a second transistor bridge in parallel to the first transistor bridge,
wherein the first transistor bridge includes a first transistor switch and a second transistor switch, connected through the first node, and
the second transistor bridge includes a third transistor switch and a fourth transistor switch connected through the second node.

16. The system of claim 15 , wherein the means for generating switching voltages at the first node and the second node of a transistor circuit with a deadtime comprises:
means for turning on or off the first and the fourth transistor switches, and the second and the third transistor switches alternately by:
means for applying a first gate voltage to the first transistor switch and the fourth transistor switch and a reverse of the first gate voltage to the second transistor switch and the third transistor switch.

17. The system of claim 15 , further comprising:
means for feeding the first voltage to the first transistor switch and the fourth transistor switch as a first gate voltage; and
means for feeding the second voltage to the second transistor switch and the third transistor switch as a second gate voltage.

18. The system of claim 16 , further comprising:
means for causing the first voltage at the first node to switch between a value equivalent to the input voltage

Assignees

• Integrated Device Tech

Inventors

• Qi Tao
• Mehas Gustavo
• Jeong Chan Young
• Gu Xinyun
• Smith Nicholaus
• Bavisi Amit D
• Sugasawara Daryl
• Lee Aihua

Classifications

• H02J7/90

  Regulation of charging or discharging current or voltage · CPC title

• H02J50/10 Primary

  using inductive coupling · CPC title

• H02M3/33569

  having several active switching elements (H02M3/3353 takes precedence) · CPC title

• H02J2207/20

  Charging or discharging characterised by the power electronics converter · CPC title

• H02M1/38

  Means for preventing simultaneous conduction of switches · CPC title