Storage device including nonvolatile memory device and operating method thereof

Patent metadata

Field	Value
Publication number	US-11004517-B2
Application number	US-201916356182-A
Country	US
Kind code	B2
Filing date	Mar 18, 2019
Priority date	Aug 14, 2018
Publication date	May 11, 2021
Grant date	May 11, 2021

Abstract

A storage device includes a nonvolatile memory device including a memory block and a memory controller. The memory block includes a first memory region connected with a first word line and a second memory region connected with a second word line. The memory controller sets a read block voltage based on a first read voltage of the first memory region. The memory controller determines a second read voltage of the second memory region based on variation information and the read block voltage.

First claim

What is claimed is:

1. A storage device comprising:
a nonvolatile memory device including at least one memory block, the at least one memory block including at least a first memory region connected to a first word line and a second memory region connected to a second word line; and
a memory controller configured to,
set a read block voltage corresponding to the memory block based on a first read voltage to be applied to the first memory region,
set variation information related to the first memory region, the second memory region, and the read block voltage based on a change of a read voltage of the first memory region and a change of a read voltage of the second memory region, and
determine a second read voltage to be applied to the second memory region based on the variation information, wherein
the memory block further includes a reference memory region connected to a reference word line;
the memory controller is further configured to,
set first offset information based on a difference between a predicted read voltage of the reference memory region and a predicted read voltage of the first memory region, and
set second offset information based on a difference between the predicted read voltage of the reference memory region and a predicted read voltage of the second memory region; and

the variation information includes the first offset information and the second offset information.

2. The storage device of claim 1 , wherein the memory controller is further configured to calculate the read block voltage based on the first read voltage and the first offset information.

3. The storage device of claim 1 , wherein the memory controller is further configured to calculate the second read voltage based on the read block voltage and the second offset information.

4. The storage device of claim 1 , wherein
the variation information includes a plurality of variation tables respectively corresponding to a plurality of conditions classified with respect to at least one deterioration factor; and
each of the plurality of variation tables includes,
first word line information generated based on a read voltage of the first memory region set according to the corresponding condition to each of the plurality of variation tables, and
second word line information generated based on a read voltage of the second memory region set according to the corresponding condition to each of the plurality of variation tables.

5. The storage device of claim 4 , wherein the memory controller is further configured to select one variation table of the plurality of variation tables based on the first read voltage and the first word line information included in each of the plurality of variation tables.

6. The storage device of claim 5 , wherein the memory controller is further configured to:
calculate the read block voltage based on the first read voltage and the first word line information included in the selected variation table; and
calculate the second read voltage based on the read block voltage and the second word line information included in the selected variation table.

7. The storage device of claim 4 , wherein the memory controller is further configured to:
detect a deterioration state of the memory block corresponding to the at least one deterioration factor; and
select one variation table of the plurality of variation tables based on the deterioration state.

8. The storage device of claim 4 , wherein the at least one deterioration factor includes at least one of a program/erase count, a read count, a retention time, a temperature, or a read disturb of the memory block.

9. The storage device of claim 1 , wherein
the variation information includes coefficient information corresponding to a desired relationship between a read voltage of the first memory region and a read voltage of the second memory region; and
the memory controller is further configured to calculate the second read voltage based on the desired relationship, the coefficient information, and the read block voltage.

10. The storage device of claim 1 , wherein
the memory controller is further configured to generate prediction model information by training a desired relationship between a read voltage of the second memory region and a read voltage of the first memory region; and
the variation information includes the generated prediction model information.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Yunjung
• Kim Chanha
• Kang Suk-Eun
• Ro Seungkyung
• Lee Kwangwoo
• Lee Juwon
• Lee Jinwook
• Lee Heewon

Classifications

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G06F3/0658

  Controller construction arrangements · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G11C29/021

  in voltage or current generators · CPC title