Offload processing using a storage slot

Patent metadata

Field	Value
Publication number	US-11003539-B2
Application number	US-201916247770-A
Country	US
Kind code	B2
Filing date	Jan 15, 2019
Priority date	Jan 15, 2019
Publication date	May 11, 2021
Grant date	May 11, 2021

Abstract

Offload processing may be provided that is not dedicated to a primary processor or a subset of primary processors. A system may have one or more offload processing devices, including one or more APUs, coupled to data storage slots of the system, which can be shared by multiple primary processors of the system. Each offload processing device may be configured to be coupled to a storage slot, for example, as if the device were a storage drive, and include an interface in conformance with a version of an NVMe specification and may have a form factor in accordance with the U.2 specification. The APU within each offload processing device may be communicatively coupled to one or more primary processors by switching fabric disposed between the one or more primary processors and the storage slot to which the offload processing device is connected.

First claim

What is claimed is:

1. A system comprising:
one or more primary processors;
one or more storage slots arranged to receive storage drives;
a switch fabric communicatively coupling the one or more storage slots to the one or more primary processors to perform I/O operations between the one or more primary processors and one or more storage drives installed in the one or more storage slots;
a processing device including an accelerated processing unit, the processing device disposed with the one or more storage slots, the accelerated processing unit communicatively coupled to the one or more primary processors; and
a memory comprising code stored thereon that, when executed, performs a method comprising:
a first primary processor of the one or more primary processors sending first data and one or more first instructions over the switch fabric to the accelerated processing unit, and
the accelerated processing unit executing the one or more first instructions on the first data,

wherein the one or more first instructions define an application, and wherein the accelerated processing unit executes the application to produce results without assistance from the first processor and communicates the results to the first processor.

2. The system of claim 1 , wherein the accelerated processing unit includes:
at least one central processing unit;
at least one graphical processing unit; and
logic to determine utilization of the at least one central processing unit and/or the at least one graphical processing unit based at least in part on a processing task to be performed.

3. The system of claim 1 , wherein the one or more primary processors includes a plurality of primary processors communicatively coupled to the accelerated processing unit.

4. The system of claim 1 , wherein the processing device has a form factor in conformance with a U.2 specification.

5. The system of claim 1 , wherein the processing device has an interface that interfaces the accelerated processing unit with the switch fabric in accordance with an NVMe specification.

6. The system of claim 1 , wherein the method further comprises:
a second primary processor of the one or more primary processors sending second data and one or more second instructions over the switch fabric to the accelerated processing unit; and
the accelerated processing unit executing the one or more second instructions on the second data.

7. The system of claim 1 , wherein during execution of the one or more first instructions, the first primary processor fails, and
wherein the accelerated processing unit continues executing the one or more first instructions during the failure of the first primary processor.

8. The system of claim 1 , wherein the system is a data storage system including one or more directors that include the one or more primary processors and one or more back-end adapters communicatively coupling the one or more directors to the accelerated processing unit across the switch fabric.

9. For a system comprising a plurality of primary processors, an accelerated processing unit physically coupled to the system by a non-volatile storage slot of the system, and a switch fabric communicatively coupling the non-volatile storage slot to each of the plurality of primary processors, a method comprising:
a first processor of the plurality of primary processors sending first data and one or more first instructions over the switch fabric to the accelerated processing unit; and
the accelerated processing unit executing the one or more first instructions on the first data,
wherein the one or more first instructions define an application, and wherein the accelerated processing unit executes the application to produce results without assistance from the first primary processor and communicates the results to the first primary processor.

10. The method of claim 9 , further comprising:
a second processor of the plurality of primary processors sending second data and one or more second instructions over the switch fabric to the accelerated processing unit; and
the accelerated processing unit executing the one or more second instructions on the second data.

11. The method of claim 9 , wherein during execution of the one or more first instructions, the first processor fails, and
wherein the accelerated processing unit continues executing the one or more first instructions during the failure of the first processor.

12. The method of claim 9 , wherein the accelerated processing unit includes at least one central processing unit and at least one graphical processing unit, and wherein the method further comprises:
determining utilization of the at least one central processing unit and/or the at least one graphical processing unit based at least in part on a processing task to be performed.

13. The method of claim 9 , wherein the accelerated processing unit is part of a processing device having a form factor in conformance with a U.2 specification.

14. The method of claim 9 , wherein the accelerated processing unit is part of a processing device having an interface that interfaces the accelerated processing unit with the switch fabric in accordance with an NVMe specification.

Assignees

• Emc Ip Holding Co Llc

Inventors

• Krasner Jon I
• Sprague Jonathan P
• Duquette Jason J

Classifications

• G06F11/1428

  with loss of hardware functionality · CPC title

• G06F11/1423 Primary

  by reconfiguration of paths · CPC title

• G06F9/5027 Primary

  the resource being a machine, e.g. CPUs, Servers, Terminals · CPC title

• G06F11/0724

  in a multiprocessor or a multi-core unit (multiprocessors per se G06F15/80) · CPC title

• G06F9/3877

  using a secondary processor, e.g. coprocessor (peripheral processor G06F13/12) · CPC title