Coalescing adjacent gather/scatter operations

Patent metadata

Field	Value
Publication number	US-11003455-B2
Application number	US-201916398183-A
Country	US
Kind code	B2
Filing date	Apr 29, 2019
Priority date	Dec 26, 2012
Publication date	May 11, 2021
Grant date	May 11, 2021

Abstract

According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.

First claim

What is claimed is:

1. A processor comprising:
a data cache to cache data;
an instruction cache to cache a first instruction, the first instruction to indicate a 128-bit operand size, the first instruction having a first field to specify a first 128-bit single instruction, multiple data (SIMD) source register of a plurality of 128-bit SIMD registers, the first instruction having a second field to specify a 64-bit general-purpose register of a plurality of 64-bit general-purpose registers to store a base address, and the first instruction to indicate a data element width of 64-bits;
an instruction fetch unit coupled to the instruction cache to fetch instructions;
a decode unit coupled to the instruction fetch unit, the decode unit to decode the instructions; and
an execution unit coupled to the decode unit, the execution unit in response to the first instruction to:
store a first structure and a second structure to a memory based on the base address, a first 64-bit data element of the first structure to include a first 64-bit data element of the first 128-bit SIMD source register, which is to be from least significant bits of the first 128-bit SIMD source register, a second 64-bit data element of the first structure to include a first 64-bit data element of a second 128-bit SIMD source register, which is to be from least significant bits of the second 128-bit SIMD source register, a third 64-bit data element of the first structure to include a first 64-bit data element of a third 128-bit SIMD source register, which is to be from least significant bits of the third 128-bit SIMD source register, wherein the first, the second, and the third 64-bit data elements of the first structure are to be consecutive data elements in the memory, a first 64-bit data element of the second structure to include a second 64-bit data element of the first 128-bit SIMD source register, a second 64-bit data element of the second structure to include a second 64-bit data element of the second 128-bit SIMD source register, and a third 64-bit data element of the second structure to include a second 64-bit data element of the third 128-bit SIMD source register, wherein the first, the second, and the third 64-bit data elements of the second structure are to be consecutive data elements in the memory, and wherein the first, the second, and the third 128-bit SIMD source registers are a sequence of registers.

2. The processor of claim 1 , wherein the first instruction has a data element width field to indicate the data element width of 64-bits.

3. The processor of claim 1 , wherein a single bit of the first instruction is to indicate the 128-bit operand size.

4. The processor of claim 1 , wherein the processor has a reduced instruction set computing (RISC) architecture.

5. A processor comprising:
a data cache to cache data;
an instruction cache to cache a first instruction, the first instruction to indicate a 128-bit operand size, the first instruction having a first field to specify a first 128-bit single instruction, multiple data (SIMD) source register of a plurality of 128-bit SIMD registers, the first instruction having a second field to specify a 64-bit general-purpose register of a plurality of 64-bit general-purpose registers to store a base address, and the first instruction to indicate a data element width of 64-bits;
an instruction fetch unit coupled to the instruction cache to fetch instructions;
a decode circuit coupled to the instruction fetch unit, the decode circuit to decode the instructions; and
an execution circuit coupled to the decode circuit, the execution circuit in response to the first instruction to:
store a first structure and a second structure to a memory based on the base address, a first 64-bit data element of the first structure to include a first 64-bit data element of the first 128-bit SIMD source register, which is to be from least significant bits of the first 128-bit SIMD source register, a second 64-bit data element of the first structure to include a first 64-bit data element of a second 128-bit SIMD source register, which is to be from least significant bits of the second 128-bit SIMD source register, a third 64-bit data element of the first structure to include a first 64-bit data element of a third 128-bit SIMD source register, which is to be from least significant bits of the third 128-bit SIMD source register, wherein the first, the second, and the third 64-bit data elements of the first structure are to be consecutive data elements in the memory, a first 64-bit data element of the second structure to include a second 64-bit data element of the first 128-bit SIMD source register, a second 64-bit data element of the second structure to include a second 64-bit data element of the second 128-bit SIMD source register, and a third 64-bit data element of the second structure to include a second 64-bit data element of the third 128-bit SIMD source register, wherein the first, the second, and the third 64-bit data elements of the second structure are to be consecutive data elements in the memory, and wherein the first, the second, and the third 128-bit SIMD source registers are a sequence of registers.

6. The processor of claim 5 , wherein the first instruction has a data element width field to indicate the data element width of 64-bits.

7. The processor of claim 5 , wherein a single bit of the first instruction is to indicate the 128-bit operand size.

8. The processor of claim 5 , wherein the processor has a reduced instruction set computing (RISC) architecture.

Assignees

• Intel Corp

Inventors

• Forsyth Andrew T
• Hickmann Brian J
• Hall Jonathan C
• Hughes Christopher J

Classifications

• G06F9/3887

  controlled by a single instruction for multiple data lanes [SIMD] · CPC title

• G06F9/30038

  using a mask · CPC title

• G06F9/3888

  controlled by a single instruction for multiple threads [SIMT] in parallel · CPC title

• G06F9/30018 Primary

  Bit or string instructions · CPC title

• G06F9/30036

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title