Power management integrated circuit including a supervisory circuit that controls a switch arranged between a node of an electrical resistance circuit and a reference potential node

Patent metadata

Field	Value
Publication number	US-11003232-B2
Application number	US-201916371458-A
Country	US
Kind code	B2
Filing date	Apr 1, 2019
Priority date	Apr 4, 2018
Publication date	May 11, 2021
Grant date	May 11, 2021

Abstract

A power management integrated circuit including a reference signal generator, a start-up unit and a supervisory circuit. The supervisory circuit includes an electrical resistance circuit connected between a first end node and a second end node; a power supply input for receiving a supply voltage, this power supply input being connected to the first end node; a low reference potential node; a comparator for comparing a reference voltage value at a first input and a divided voltage value at a second input connected to an internal electrical node of the electrical resistance circuit, the comparator can output a monitoring signal. The supervisory circuit includes a switch controlled by the start-up unit so that the switch is selectively closed and opened based on a detected operational state of the reference signal generator indicating a normal functioning phase of the power management circuit.

First claim

The invention claimed is:

1. A power management circuit, comprising:
a reference signal generator configured to provide a reference signal;
a start-up unit,
the start-up unit having a first sensing input for detecting whether a supply voltage provided to the power management circuit is above a threshold voltage,
the start-up unit being configured to:
generate, during a start-up phase, a start-up current for starting-up the reference signal generator when the supply voltage is detected to be above the threshold voltage, and
stop generating the start-up current when the power management circuit enters a steady state operational phase, and

during the steady state operational phase, the start-up unit having a second sensing input connected to the reference signal generator and receiving from the reference signal generator a state signal indicating whether the power management circuit is in the steady state operational phase; and

a supervisory circuit comprising:
an electrical resistance circuit comprising a set of electrical resistance elements connected between a first end node and a second end node of the electrical resistance circuit;
a high power supply input arranged for receiving the supply voltage and connected to the first end node of the electrical resistance circuit;
a reference potential node defining a low power supply input; and
a comparator for comparing the reference signal at a first input and an intermediate electrical value at a second input, the second input being connected to an internal electrical node of the electrical resistance circuit, the internal electrical node being located between two consecutive electrical resistance elements of the electrical resistance circuit, the comparator being configured to output a monitoring signal at a comparator output for monitoring a supply of a given electrical level related to the intermediate electrical value; wherein

the supervisory circuit further comprises a switch arranged between the second end node of the electrical resistance circuit and the reference potential node, the switch being open when not powered,
the start-up unit is configured to control the switch in order to maintain the switch in an open state in the start-up phase and to close the switch when the power management circuit terminates the start-up phase and enters the steady state operational phase, as well as to maintain the switch in an closed state during the steady state operational phase, and
the comparator output is connected to a first input of a logic AND gate, while a second input of the logic AND gate is connected to a reset signal generator for receiving a reset signal, an output of the AND gate being connected to an output of the supervisory circuit.

2. The power management circuit according to claim 1 , wherein the switch is an n-type metal-oxide-semiconductor field effect transistor.

3. The power management circuit according to claim 1 , wherein
the reference signal generator comprises a reference current generator and a reference voltage generator,
the first sensing input is a voltage sensing input and the second sensing input is a current sensing input, and
the reference signal is a reference voltage signal and the state signal is a current signal indicating whether the reference signal generator is in an operational state.

4. The power management circuit according to claim 1 , wherein
the electrical resistance circuit comprises a given number of internal electrical nodes, each of the internal electrical nodes being located between two consecutive electrical resistance elements, and

each of the internal electrical nodes is connected to a respective comparator for providing to the respective comparator a respective intermediate electrical value.

5. The power management circuit according to claim 4 , wherein a low reference potential node is at zero electric potential.

6. The power management circuit according to claim 1 , wherein
the supervisory circuit further comprises a protection circuit between the electrical resistance circuit and the comparator for disconnecting the comparator from the electrical resistance circuit when the intermediate electrical value is above a threshold level.

Assignees

• Em Microelectronic Marin Sa

Inventors

• Saby Jerome
• Contaldo Matteo
• Theoduloz Yves

Classifications

• H02M1/36

  Means for starting or stopping converters · CPC title

• G06F1/28 Primary

  Supervision thereof, e.g. detecting power-supply failure by out of limits supervision · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F1/3234

  Power saving characterised by the action undertaken · CPC title

• G06F1/3287

  by switching off individual functional units in the computer system · CPC title