Sigma-delta analog-to-digital converter

Patent metadata

Field	Value
Publication number	US-10998917-B1
Application number	US-202016929084-A
Country	US
Kind code	B1
Filing date	Jul 14, 2020
Priority date	Jul 14, 2020
Publication date	May 4, 2021
Grant date	May 4, 2021

Abstract

A sigma-delta analog-to-digital converter (ADC) includes a feed-forward circuit, a finite-impulse-response (FIR) digital-to-analog converter (DAC), and a decimation filter. The feed-forward circuit is configured to receive an analog input signal and a feedback signal and generate a set of digital signals. Each feedback element of the FIR DAC includes a flip-flop and a reset circuit. The reset circuit is configured to receive a corresponding reset signal of a set of reset signals and output a reference output signal when the corresponding reset signal is deactivated. The reset signal of each feedback element is deactivated sequentially after each cycle of a clock signal that is received by the flip-flop associated with a corresponding reset circuit of each feedback element. The feedback signal is generated based on the reference output signal. The decimation filter is configured to generate a digital output signal based on the set of digital signals.

First claim

The invention claimed is:

1. A sigma-delta analog-to-digital converter (ADC), comprising:
a feed-forward circuit that is configured to receive a set of analog signals and a refresh signal, and generate a set of digital signals, wherein the set of analog signals includes an analog input signal and a feedback signal;
a first finite-impulse-response (FIR) digital-to-analog converter (DAC) that is coupled with the feed-forward circuit, and configured to receive the set of digital signals and a clock signal, and generate the feedback signal, wherein the first FIR DAC comprises a set of feedback elements, and wherein each feedback element comprises:
a flip-flop that is configured to receive a first input signal and generate a set of flop-output signals, wherein the first input signal is based on the set of digital signals; and
a reset circuit that is coupled with the flip-flop, and configured to receive a set of reference signals, the set of flop-output signals, and a corresponding reset signal of a set of reset signals, and output a reference output signal based on the corresponding reset signal, wherein the reset circuit of each feedback element outputs the reference output signal sequentially after each cycle of the clock signal, and wherein the feedback signal is generated based on the reference output signal; and

a decimation filter that is coupled with the feed-forward circuit, and configured to receive the set of digital signals and the refresh signal, and generate a digital output signal.

2. The sigma-delta ADC of claim 1 , wherein the feed-forward circuit comprises a first adder that is configured to receive the analog input signal and the feedback signal, and generate a first analog output signal.

3. The sigma-delta ADC of claim 2 , wherein the feed-forward circuit further comprises a loop filter that is coupled with the first adder, and configured to receive the first analog output signal, a compensation signal, and the refresh signal, and generate an integrated analog signal, and wherein the set of analog signals further includes the compensation signal.

4. The sigma-delta ADC of claim 3 , wherein the loop filter comprises:
a first integrator that is coupled with the first adder, and configured to receive the first analog output signal and the refresh signal, integrate the first analog output signal, and generate a second analog output signal;
a first gain stage that is coupled with the first integrator, and configured to receive the second analog output signal and generate a third analog output signal;
a second integrator that is coupled with the first integrator, and configured to receive the second analog output signal and the refresh signal, integrate the second analog output signal, and generate a fourth analog output signal;
a second adder that is coupled with the first gain stage and the second integrator, and configured to receive the third analog output signal, the fourth analog output signal, and the compensation signal, and generate a fifth analog output signal; and
a third integrator that is coupled with the second adder, and configured to receive the fifth analog output signal and the refresh signal, integrate the fifth analog output signal, and generate the integrated analog signal, wherein the first through third integrators generate the second analog output signal, the fourth analog output signal, and the integrated analog signal, respectively, when the refresh signal is deactivated.

5. The sigma-delta ADC of claim 3 , wherein the feed-forward circuit further comprises a quantizer that is coupled with the loop filter, and configured to receive the integrated analog signal and generate the set of digital signals.

6. The sigma-delta ADC of claim 5 , further comprising:
a second FIR DAC that is coupled with the quantizer and the loop filter, and configured to receive the set of digital signals, the clock signal, the set of reset signals, and the set of reference signals, and generate the compensation signal; and
a control circuit that is coupled with the loop filter, the first FIR DAC, the decimation filter, and the second FIR DAC, and configured to generate the clock signal, the set of reference signals, the refresh signal, and the set of reset signals such that each reset signal is deactivated sequentially after each cycle of the clock signal.

7. The sigma-delta ADC of claim 1 , wherein the first FIR DAC further comprises:
a first switch that is coupled with the feed-forward circuit, and configured to receive a first digital signal of the set of digital signals, and a first reference signal of the set of reference signals, and output the first reference signal when the first digital signal is activated, wherein the first digital signal is a single-bit digital signal; and
a second switch that is coupled with the feed-forward circuit, and configured to receive a second digital signal of the set of digital signals and a second reference signal of the set of reference signals, and output the second reference signal when the second digital signal is activated, wherein the second digital signal is an inverted version of the first digital signal, and wherein the second digital signal is a single-bit digital signal.

8. The sigma-delta ADC of claim 7 , wherein the first FIR DAC further comprises a third adder that is coupled with the first and second switches and the set of feedback elements, and configured to receive the first and second reference signals when the first and second switches are activated, respectively, and the reference output signal from the reset circuit of each feedback element, and generate a sixth analog output signal.

9. The sigma-delta ADC of claim 8 , wherein the first FIR DAC further comprises a second gain stage that is coupled with the third adder, and configured to receive the sixth analog output signal and generate the feedback signal.

10. The sigma-delta ADC of claim 1 , wherein the first input signal is at least one of a first digital signal of the set of digital signals and a corresponding flop-output signal of a previous feedback element of the set of feedback elements.

11. The sigma-delta ADC of claim 1 , wherein the reset circuit comprises:
a first logic gate that is configured to receive the corresponding reset signal and generate an inverted reset signal;
a second logic gate that is coupled with the flip-flop and the first logic gate, and configured to receive a first flop-output signal of the set of flop-output signals and the inverted reset signal and generate a first logic signal;
a third switch that is coupled with the second logic gate, and configured to receive the first logic signal and a first reference signal of the set of reference signals, and output the first reference signal as the reference output signal when the first logic signal is activated;
a third logic gate that is coupled with the flip-flop and the first logic gate, and configured to receive a second flop-output signal of the set of flop-output signals and the inverted reset signal and generate a second logic signal, wherein the second flop-output signal is an inverted version of the first flop-output signal; and
a fourth switch that is coupled with the third logic gate, and configured to receive the second logic signal and a second reference signal of the set of reference signals, and output the second reference signal as the reference output signal when the second logic signal is activated.

12. The sigma-delta ADC of claim 1 , wherein the set of reset signals includes first through Nth reset signals, and wherein the refresh signal and the set of reset signals are activated at a start of a first cycle of the clock signal, the refresh signal is

Assignees

• Nxp Bv

Inventors

• Singh Kamlesh

Classifications

• H03M3/504

  the final digital/analogue converter being constituted by a finite impulse response [FIR] filter, i.e. FIRDAC · CPC title

• H03M3/464

  Details of the digital/analogue conversion in the feedback path · CPC title

• H03M3/462

  Details relating to the decimation process (decimation filters in general H03H17/0416, H03H17/0621) · CPC title

• H03M3/454

  with distributed feedback, i.e. with feedback paths from the quantiser output to more than one filter stage · CPC title

• H03M3/39 Primary

  Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators (of digital delta-sigma modulators H03M7/3004) · CPC title