T-coil enhanced ESD protection with passive equalization

Patent metadata

Field	Value
Publication number	US-10998720-B2
Application number	US-201715788650-A
Country	US
Kind code	B2
Filing date	Oct 19, 2017
Priority date	Oct 19, 2017
Publication date	May 4, 2021
Grant date	May 4, 2021

Abstract

An Electro-Static Discharge (ESD) protection circuit is disclosed. In some implementations, the ESD protection circuit includes a first ESD diode, a second ESD diode, a passive equalization network and a programmable resistor network. The first ESD diode is coupled to the passive equalization network. The programmable resistor network is coupled between the passive equalization network and the second ESD diode. The programmable resistor network can be programmed to place the ESD protection circuit in one of a plurality of receiver modes based on a type of a transmitter from which the receiver is receiving signals.

First claim

What is claimed is:

1. An electro-static discharge (ESD) protection circuit in a receiver, comprising:
a first ESD diode;
a second ESD diode;
a passive equalization network comprising
a capacitor having a first terminal and a second terminal, the first terminal coupled to the first ESD diode, and
a resistor coupled in parallel to the capacitor at the first terminal and the second terminal; and

a programmable resistor network coupled between the passive equalization network and the second ESD diode, wherein the passive equalization network is coupled between the first ESD diode and the programmable resistor network, and the second terminal of the capacitor of the passive equalization network is coupled to the programmable resistor network.

2. The ESD protection circuit of claim 1 , further comprising:
a T-coil network coupled between the first ESD diode and a pad through which signals are received.

3. The ESD protection circuit of claim 1 , wherein the programmable resistor network is configured to level shift a common mode voltage of signals from the first ESD diode.

4. An electro-static discharge (ESD) protection circuit in a receiver, comprising:
a first ESD diode;
a second ESD diode;
a passive equalization network; and
a programmable resistor network coupled between the passive equalization network and the second ESD diode, wherein the passive equalization network is coupled between the first ESD diode and the programmable resistor network, wherein the programmable resistor network comprises
a first resistor, a second resistor, a third resistor, and a fourth resistor coupled together at a node, wherein the passive equalization network is coupled to the node,
a first n-type transistor and a second n-type transistor, wherein the first n-type transistor and the first resistor are coupled in series between the node and a power supply, and the second n-type transistor and the second resistor are coupled in series between the node and the power supply, and
a first p-type transistor and a second p-type transistor, wherein the first p-type transistor and the third resistor are coupled in series between the node and ground, and the second p-type transistor and the fourth resistor are coupled in series between the node and ground.

5. The ESD protection circuit of claim 4 , wherein the programmable resistor network is programmable to place the receiver in one of a plurality of receiver modes based on a type of a transmitter from which the receiver is receiving signals.

6. The ESD protection circuit of claim 5 , wherein the programmable resistor network is configured to be programmed by turning on or turning off the first and second n-type transistors and the first and second p-type transistors.

7. A system, comprising:
a plurality of pads configured to receive signals; and
a receiver having an analog front end, the analog front end comprising
a variable gain amplifier;
an electro-static discharge (ESD) protection circuit coupled between the variable gain amplifier and the plurality of pads, the ESD protection circuit comprising
a first ESD diode;
a second ESD diode;
a passive equalization network, comprising
a capacitor having a first terminal and a second terminal, the first terminal coupled to the first ESD diode, and the second terminal coupled to the programmable resistor network, and
a resistor coupled in parallel to the capacitor at the first terminal and the second terminal; and

a programmable resistor network coupled between the passive equalization network and the second ESD diode, wherein the passive equalization network is coupled between the first ESD diode and the programmable resistor network.

8. The system of claim 7 , wherein the ESD protection circuit further comprises:
a T-coil network coupled between the first ESD diode and the plurality of pads.

9. The system of claim 7 , wherein the programmable resistor network is configured to level shift a common mode voltage of signals from the first ESD diode.

10. A system, comprising:
a plurality of pads configured to receive signals; and
a receiver having an analog front end, the analog front end comprising
a variable gain amplifier;
the electro-static discharge (ESD) protection circuit coupled between the variable gain amplifier and the plurality of pads, the ESD protection circuit comprising
a first ESD diode;
a second ESD diode;
a passive equalization network; and
a programmable resistor network coupled between the passive equalization network and the second ESD diode, wherein the passive equalization network is coupled between the first ESD diode and the programmable resistor network, wherein the programmable resistor network comprises:

a first resistor, a second resistor, a third resistor, and a fourth resistor coupled together at a node, wherein the passive equalization network is coupled to the node,
a first n-type transistor and a second n-type transistor, wherein the first n-type transistor and the first resistor are coupled in series between the node and a power supply, and the second n-type transistor and the second resistor are coupled in series between the node and the power supply, and
a first p-type transistor and a second p-type transistor, wherein the first p-type transistor and the third resistor are coupled in series between the node and ground, and the second p-type transistor and the fourth resistor are coupled in series between the node and ground.

11. The system of claim 10 , wherein the programmable resistor network is programmable to place the receiver in one of a plurality of receiver modes based on a type of a transmitter from which the receiver is receiving signals.

12. The system of claim 11 , wherein the programmable resistor network is configured to be programmed by turning on or turning off the first and second n-type transistors and the first and second p-type transistors.

Assignees

• Qualcomm Inc

Inventors

• Yuan Xiaobin
• Cox Carrie Ellen
• Natonio Joseph
• Fan Siqi

Classifications

• H10D89/911

  using passive elements as protective elements · CPC title

• H10D89/611 Primary

  using diodes as protective elements · CPC title

• H04L25/03031

  using only passive components (H04L25/03025 takes precedence) · CPC title

• H04L25/03057

  with a recursive structure (H04L25/03031 takes precedence) · CPC title

• H02H9/046

  responsive to excess voltage appearing at terminals of integrated circuits · CPC title