Interlayer dielectric for non-planar transistors

Patent metadata

Field	Value
Publication number	US-10998445-B2
Application number	US-202016877355-A
Country	US
Kind code	B2
Filing date	May 18, 2020
Priority date	Dec 6, 2011
Publication date	May 4, 2021
Grant date	May 4, 2021

Abstract

The present description relates the formation of a first level interlayer dielectric material layer within a non-planar transistor, which may be formed by a spin-on coating technique followed by oxidation and annealing. The first level interlayer dielectric material layer may be substantially void free and may exert a tensile strain on the source/drain regions of the non-planar transistor.

First claim

What is claimed is:

1. An integrated circuit (IC) structure, comprising:
a fin having a source and a drain;
a transistor gate formed on the fin between the source and the drain, wherein the transistor gate comprises a gate electrode, a gate dielectric between the gate electrode and the fin, and a pair of sidewalls formed on opposing sides of the gate electrode;
spacers on the pair of sidewalls;
an adhesion liner contacting the spacers, the source, and the drain;
a dielectric layer contacting the adhesion liner, wherein an upper portion of the dielectric layer has a higher density than a lower portion of the dielectric layer, wherein both the densified portion of the dielectric layer and a non-densified portion of the dielectric layer contact the adhesion liner; and
at least one contact extending though the dielectric layer contacting at least one of the source and the drain.

2. The integrated circuit (IC) structure of claim 1 , wherein the upper portion of the dielectric layer comprises an annealed portion of the dielectric layer.

3. The integrated circuit (IC) structure of claim 1 , wherein the upper portion of the dielectric layer comprises an oxidized portion of the dielectric layer.

4. The integrated circuit (IC) structure of claim 1 , wherein the upper portion of the dielectric layer comprises an annealed and oxidized portion of the dielectric layer.

5. The integrated circuit (IC) structure of claim 1 , wherein the fin comprises silicon.

6. The integrated circuit (IC) structure of claim 1 , wherein the dielectric layer comprises silicon and oxygen.

7. The integrated circuit (IC) structure of claim 6 , wherein the dielectric layer comprises silicon oxide.

8. The integrated circuit (IC) structure of claim 1 , wherein the transistor gate is non-planar.

9. The integrated circuit (IC) structure of claim 1 , wherein the source and the drain are non-planar.

10. A method of forming an integrated circuit (IC) structure, comprising:
forming a fin;
forming a source and a drain in the fin;
forming a transistor gate on the fin between the source and the drain, wherein the transistor gate comprises a gate electrode, a gate dielectric between the gate electrode and the fin and a pair of sidewalls formed on opposing sides of the gate electrode;
forming spacers on the pair of sidewalls;
forming an adhesion liner contacting the spacers, the source, and the drain;
forming a dielectric layer contacting the adhesion liner;
forming a densified portion of the dielectric layer resulting in a densified portion of the dielectric layer and a non-densified portion of the dielectric layer, wherein both the densified portion of the dielectric layer and a non-densified portion of the dielectric layer contact the adhesion liner; and
forming at least one contact extending though the dielectric layer contacting at least one of the source and the drain.

11. The method of claim 10 , wherein forming the densified portion of the dielectric layer comprises annealing the portion of the dielectric.

12. The method of claim 11 , wherein annealing the portion of the dielectric layer comprises annealing the dielectric layer with high density plasma in an inert atmosphere.

13. The method of claim 10 , wherein forming the densified portion of the dielectric layer comprises oxidizing the portion of the dielectric layer.

14. The method of claim 13 , wherein oxidizing the portion of the dielectric layer comprises heating the dielectric layer in a steam atmosphere.

15. The method of claim 10 , wherein forming the densified portion of the dielectric layer comprises oxidizing and annealing the portion of the dielectric layer.

16. The method of claim 10 , wherein the fin comprises silicon.

17. The method of claim 10 , wherein forming the dielectric layer comprises forming the dielectric layer comprising silicon and oxygen.

18. The method of claim 17 , wherein forming the dielectric layer comprises forming a silicon oxide dielectric layer.

19. The method of claim 10 , wherein forming the transistor gate comprises forming a non-planar transistor gate.

20. The method of claim 10 , wherein forming the source and the drain comprises forming a non-planar source and a non-planar drain.

Assignees

• Intel Corp

Inventors

• Pradhan Sameer S
• Luce Jeanne L

Classifications

• H10P14/6342

  Liquid deposition, e.g. spin-coating, sol-gel techniques or spray coating · CPC title

• H10P14/6544

  to change the morphology of the insulating materials, e.g. transformation of an amorphous layer into a crystalline layer · CPC title

• H10P14/6532

  by exposure to a plasma · CPC title

• H10P14/6529

  by exposure to a gas or vapour · CPC title

• H10P14/6519

  the substance being oxygen · CPC title