Efficient heat-sinking in PIN diode

Patent metadata

Field	Value
Publication number	US-10998252-B2
Application number	US-202016791315-A
Country	US
Kind code	B2
Filing date	Feb 14, 2020
Priority date	Dec 31, 2018
Publication date	May 4, 2021
Grant date	May 4, 2021

Abstract

The thermal impedance of p-i-n diodes integrated on semiconductor-on-insulator substrates can be reduced with thermally conducting vias that shunt heat across thermal barriers such as, e.g., the thick top oxide cladding often encapsulating the p-i-n diode. In various embodiments, one or more thermally conducting vias extend from a top surface of the intrinsic diode layer to a metal structure connected to the doped top layer of the diode, and/or from that metal structure down to at least the semiconductor device layer of the substrate.

First claim

What is claimed is:

1. A device comprising:
a silicon-on-insulator substrate comprising a silicon handle, a buried silicon dioxide layer disposed on top of the silicon handle, and a silicon device layer disposed on top of the buried silicon dioxide layer;
a top silicon dioxide cladding disposed on the silicon device layer;
a p-i-n diode embedded in the top silicon dioxide cladding layer, the p-i-n diode being made of III-V compound semiconductor material and comprising a doped top layer, an intrinsic layer, and a doped bottom layer;
a metal structure embedded in the top silicon dioxide cladding and electrically connected to the doped top layer; and
one or more thermal metal vias extending from the metal structure through the top silicon dioxide cladding at least to the silicon device layer, but not extending through the buried silicon dioxide layer to the silicon handle.

2. The device of claim 1 , wherein the one or more thermal vias contact the silicon device layer and wherein the doped bottom layer is electrically isolated from the silicon device layer by a thin silicon dioxide layer forming an integral part of the top silicon dioxide cladding.

3. The device of claim 2 , further comprising one or more isolation channels formed in the semiconductor device layer surrounding the p-i-n diode and the one or more thermal vias.

4. The device of claim 1 , wherein the one or more thermal metal vias extend through openings in the silicon device layer partially into the buried oxide layer and are electrically isolated from the silicon device layer.

5. The device of claim 1 , wherein a total cross-sectional area of the one or more thermal metal vias parallel to a plane of the silicon-on-insulator substrate exceeds an area of the intrinsic layer of the p-i-n diode.

6. The device of claim 1 , wherein the one or more thermal metal vias are first thermal vias, the device further comprising:
one or more second thermal metal vias extending from a top surface of the intrinsic layer to the metal structure.

7. The device of claim 6 , wherein the doped top layer forms a ridge on top of the intrinsic layer, the one or more second vias being laterally offset from the ridge.

8. The device of claim 1 , wherein the doped top layer is a p-type layer and the doped bottom layer is an n-type layer.

9. The device of claim 1 , wherein the thermal vias comprise at least one of gold or aluminum.

10. A device comprising:
a silicon-on-insulator substrate comprising a silicon handle, a buried silicon dioxide layer disposed on top of the silicon handle, and a silicon device layer disposed on top of the buried silicon dioxide layer;
a top silicon dioxide cladding disposed on the silicon device layer;
a p-i-n diode embedded in the top silicon dioxide cladding layer, the p-i-n diode being made of semiconductor compound material and comprising a doped top layer, an intrinsic layer, and a doped bottom layer;
a metal structure embedded in the top silicon dioxide cladding and electrically connected to the doped top layer; and
one or more thermal metal vias extending from a top surface of the intrinsic layer to the metal structure.

11. The device of claim 10 , wherein the doped top layer forms a ridge on top of the intrinsic layer, the one or more thermal metal vias being laterally offset from the ridge.

12. The device of claim 10 , wherein the doped top layer is a p-type layer and the doped bottom layer is an n-type layer.

13. The device of claim 10 , wherein the thermal metal vias comprise at least one of gold or aluminum.

14. The device of claim 10 , wherein the p-i-n diode comprises a III-V compound semiconductor material.

15. A method comprising:
forming a p-i-n diode embedded within a top oxide cladding on a silicon-on-insulator substrate, the p-i-n diode comprising doped top and bottom layers and an intrinsic layer therebetween;
embedding, in the top oxide cladding, metal layers for connection to first and second electrical nodes;
forming, in the top oxide cladding, electrical vias connecting the doped top and bottom layers to the metal layers; and
forming, in the top oxide cladding, one or more thermal vias for shunting heat across at least a portion of the top oxide cladding between the metal layers and at least one of the doped bottom layer and a silicon device layer of the substrate.

16. The method of claim 15 , wherein forming the electrical vias and the one or more thermal vias comprises:
etching electrical via holes and one or more thermal via holes; and
filling the electrical via holes and the one or more thermal via holes with one or more thermally conductive materials.

17. The method of claim 16 , wherein at least one of the electrical via holes and at least one of the one or more thermal via holes are etched simultaneously.

18. The method of claim 16 , wherein the electrical via holes and the one or more thermal via holes are filled with a same metal.

19. The method of claim 15 , further comprising, prior to forming the p-i-n diode, etching one or more openings through the silicon device layer of the silicon-on-insulator substrate, wherein the one or more thermal vias comprise one or more first thermal vias extending through the openings partially into a buried oxide layer underneath.

20. The method of claim 15 , wherein the one or more thermal vias comprise one or more first thermal vias ending at the silicon device layer, and wherein the p-i-n diode is formed on top of an insulating layer disposed on the silicon-on-insulator substrate.

Assignees

• Juniper Networks Inc

Inventors

• Norberg Erik Johan
• Dalvand Naser
• Fish Gregory Alan

Classifications

• H10W40/10

  Arrangements for heating · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W40/228

  the projecting parts being wire-shaped or pin-shaped · CPC title