Inductor

Patent metadata

Field	Value
Publication number	US-10998115-B2
Application number	US-202016822174-A
Country	US
Kind code	B2
Filing date	Mar 18, 2020
Priority date	Dec 13, 2016
Publication date	May 4, 2021
Grant date	May 4, 2021

Abstract

An inductor includes a support member, a plurality of conductor patterns disposed on at least one surface of the support member and supported by the support member, and an insulating structure interposed between conductor patterns adjacent each other among the plurality of conductor patterns, the insulating structure including a first insulating layer and a second insulating layer disposed on the first insulating layer, the second insulating layer covering side and upper surfaces of the conductor patterns, the second insulating layer being continuously formed along the side and upper surfaces of the conductor pattern, depending on external shapes of the side and upper surfaces of the conductor pattern disposed below the second insulating layer.

First claim

What is claimed is:

1. An inductor comprising:
a support member;
a plurality of conductor patterns disposed on at least one surface of the support member and supported by the support member; and
an insulating structure interposed between conductor patterns adjacent each other among the plurality of conductor patterns, the insulating structure including a first insulating layer and a second insulating layer disposed on the first insulating layer, the second insulating layer covering side and upper surfaces of the conductor patterns, the second insulating layer being continuously formed along the side and upper surfaces of the conductor patterns, depending on external shapes of the side and upper surfaces of the conductor patterns disposed below the second insulating layer,
wherein a width of an interface between the first insulating layer and the support member is wider than a width of an interface between the first insulating layer and the second insulating layer, and
a thickness of an area of the second insulating layer covering the upper surfaces of the conductor patterns is less than a thickness of at least one area of the first insulating layer, interposed between said conductor patterns adjacent each other, covering the side surfaces of the conductor patterns.

2. The inductor of claim 1 , wherein an average width of the first insulating layer is wider than that of the second insulating layer.

3. The inductor of claim 1 , wherein the first insulating layer contains an epoxy based resin, and the second insulating layer contains a perylene based resin.

4. The inductor of claim 1 , wherein the conductor patterns have an aspect ratio (AR) of 3.0 or more.

5. The inductor of claim 1 , wherein an average thickness of the conductor patterns ranges from 100 μm to 300 μm, inclusive.

6. The inductor of claim 1 , wherein at least one of the conductor patterns includes at least three conductor layers comprising first to third conductor layers,
the first conductor layer being a seed layer contacting the at least one surface of the support member and formed of an isotropic plating layer,
the second conductor layer enclosing an outer surface of the first conductor layer and formed of an anisotropic plating layer,
the third conductor layer disposed on the second conductor layer and formed of an anisotropic plating layer, and
wherein the second insulating layer contacts only an outer surface of the third conductor layer or simultaneously contacts external surfaces of the second and third conductor layers.

7. The inductor of claim 1 , wherein a space between portions of the first insulating layer adjacent each other is filled with a portion of the conductor patterns.

8. The inductor of claim 1 , wherein the support member includes a via penetrating from the at least one surface of the support member to another surface thereof, and the via electrically connects the conductor patterns disposed on the at least one surface of the support member and a conductor pattern disposed on the another surface thereof to each other.

9. The inductor of claim 1 , wherein the thickness of the area of the second insulating layer covering the upper surfaces of the conductor patterns is less than a thickness of at least one area of the second insulating layer, interposed between said conductor patterns adjacent each other, covering the side surfaces of the conductor patterns.

10. The inductor of claim 1 , wherein the conductor patterns include first and second conductor layers, and the first conductor layer is a seed layer contacting the at least one surface of the support member and is formed of an isotropic plating layer.

11. The inductor of claim 10 , wherein an upper surface of the first conductor layer is positioned lower than an upper surface of the first insulating layer.

12. The inductor of claim 10 , wherein the second conductor layer is disposed on an upper surface of the first conductor layer and formed of an anisotropic plating layer.

13. The inductor of claim 1 , wherein a distance from the at least one surface of the support member to an upper surface of the first insulating layer supported by the support member is greater than or equal to ⅓ of a thickness of the conductor patterns contacting the first insulating layer.

14. The inductor of claim 13 , wherein the distance from the at least one surface of the support member to the upper surface of the first insulating layer supported by the support member is less than or equal to 9/10 of the thickness of the conductor patterns contacting the first insulating layer.

Assignees

• Samsung Electro Mech

Inventors

• Choi Woon Chul

Classifications

• H01F27/32

  Insulating of coils, windings, or parts thereof · CPC title

• H01F27/245 Primary

  made from sheets, e.g. grain-oriented (H01F27/26 takes precedence) · CPC title

• H01F17/0013 Primary

  with stacked layers · CPC title

• H01F5/003 Primary

  Printed circuit coils · CPC title

• H01F2027/2809

  on stacked layers · CPC title