Gate driver and organic light-emitting display device including same

Patent metadata

Field	Value
Publication number	US-10997925-B2
Application number	US-201916557088-A
Country	US
Kind code	B2
Filing date	Aug 30, 2019
Priority date	Sep 3, 2018
Publication date	May 4, 2021
Grant date	May 4, 2021

Abstract

The present disclosure relates to a gate driver and an organic light-emitting display device including same. A gate driver according to an embodiment of the present disclosure includes a plurality of stages. Each of the stages includes: a first pull-up transistor configured to output a carry clock to a first output terminal as a carry signal while a Q node is bootstrapped to a voltage higher than a gate on voltage; a second pull-up transistor configured to output a scan clock to a second output terminal as a scan signal while the Q node is bootstrapped; and holding transistors configured to operate based on a voltage of a QB node, which QB node is charged and discharged in a manner reverse to that of the Q node. The holding transistors are connected to the second output terminal and the Q node, and the holding transistors are electrically isolated from the first output terminal.

First claim

The invention claimed is:

1. A gate driver, comprising:
a plurality of stages, each of the stages including:
a first pull-up transistor configured to output a carry clock to a first output terminal as a carry signal while a Q node is bootstrapped to a voltage higher than a gate on voltage;
a second pull-up transistor configured to output a scan clock to a second output terminal as a scan signal while the Q node is bootstrapped; and
holding transistors configured to operate based on a voltage of a QB node, the QB node configured to be charged and discharged in a manner reverse to charging and discharging of the Q node, and
a sensing line selector configured to store a first preceding carry input signal from a first preceding one of the stages at an M node according to a pixel line selection signal and to activate the Q node to the gate on voltage according to a voltage of the M node and a sensing start signal,
wherein the holding transistors are connected to the second output terminal and the Q node, and the holding transistors are electrically isolated from the first output terminal.

2. The gate driver of claim 1 , wherein the holding transistors comprise:
a first holding transistor configured to connect the second output terminal to a low power supply voltage terminal supplying a gate off voltage while the gate on voltage is applied to the QB node; and
a second holding transistor configured to connect the Q node to the low power supply voltage terminal while the gate on voltage is applied to the QB node.

3. The gate driver of claim 2 , wherein each of the stages further includes an input transistor for directly applying a second preceding carry signal input from a second preceding one of the plurality of stages to the Q node to activate the Q node to the gate on voltage.

4. The gate driver of claim 3 , wherein the input transistor is diode-connected between an input terminal of the second preceding carry signal and the Q node.

5. The gate driver of claim 4 , wherein a gate electrode and a first electrode of the input transistor are connected to the input terminal of the second preceding carry signal, and a second electrode of the input transistor is connected to the Q node.

6. The gate driver of claim 5 , wherein a ripple discharge path is formed between the input terminal of the second preceding carry signal and the Q node and between the Q node and the low power supply voltage terminal while the gate on voltage is applied to the QB node.

7. The gate driver of claim 1 , wherein the pixel line selection signal is applied to one of the stages during a vertical active period in which image data is written in one frame.

8. The gate driver of claim 7 , wherein the sensing start signal is applied to the one stage during a vertical blank period following the vertical active period, in which image data is not written.

9. The gate driver of claim 1 , wherein the sensing line selector comprises:
a first transistor that is turned on according to the pixel line selection signal to apply the first preceding carry signal to the M node;
a capacitor storing the first preceding carry signal applied to the M node; and
second and third transistors serially connected between a high power supply voltage terminal supplying the gate on voltage and the Q node, the second and third transistors configured to apply the gate on voltage to the Q node according to the voltage of the M node and the sensing start signal.

10. An organic light-emitting display device, comprising:
a gate driver having a plurality of stages, each of the stages including:
a first pull-up transistor configured to output a carry clock to a first output terminal as a carry signal while a Q node is bootstrapped to a voltage higher than a gate on voltage;
a second pull-up transistor configured to output a scan clock to a second output terminal as a scan signal while the Q node is bootstrapped; and
holding transistors configured to operate based on a voltage of a QB node, the QB node configured to be charged and discharged in a manner reverse to charging and discharging of the Q node, the holding transistors being connected to the second output terminal and the Q node, the holding transistors being electrically isolated from the first output terminal; and
a sensing line selector configured to store a first preceding carry signal input from a first preceding one of the stages at an M node according to a pixel line selection signal and to activate the Q node to the gate on voltage according to a voltage of the M node and a sensing start signal; and
a plurality of pixels connected to the gate driver through a plurality of gate lines.

11. The organic light-emitting display device of claim 10 , wherein the holding transistors comprise:
a first holding transistor configured to connect the second output terminal to a low power supply voltage terminal supplying a gate off voltage while the gate on voltage is applied to the QB node; and
a second holding transistor configured to connect the Q node to the low power supply voltage terminal while the gate on voltage is applied to the QB node.

12. The organic light-emitting display device of claim 11 , wherein each of the stages further includes an input transistor for directly applying a second preceding carry signal input from a second preceding one of the plurality of stages to the Q node to activate the Q node to the gate on voltage.

13. The organic light-emitting display device of claim 12 , wherein the input transistor is diode-connected between an input terminal of the second preceding carry signal and the Q node.

14. The organic light-emitting display device of claim 13 , wherein a gate electrode and a first electrode of the input transistor are connected to the input terminal of the second preceding carry signal, and a second electrode of the input transistor is connected to the Q node.

15. The organic light-emitting display device of claim 14 , wherein a ripple discharge path is formed between the input terminal of the second preceding carry signal and the Q node and between the Q node and the low power supply voltage terminal while the gate on voltage is applied to the QB node.

16. The organic light-emitting display device of claim 10 , wherein the pixel line selection signal is applied to one of the stages during a vertical active period in which image data is written in one frame.

17. The organic light-emitting display device of claim 16 , wherein the sensing start signal is applied to the one stage during a vertical blank period following the vertical active period, in which image data is not written.

18. The organic light-emitting display device of claim 10 , wherein the sensing line selector comprises:
a first transistor that is turned on according to the pixel line selection signal to apply the first preceding carry signal to the M node;
a capacitor storing the first preceding carry signal applied to the M node; and
second and third transistors serially connected between a high power supply voltage terminal supplying the gate on voltage and the Q node, the second and third transistors configured to apply the gate on voltage to the Q node according to the voltage of the M node and the sensing start signal.

Assignees

• Lg Display Co Ltd

Inventors

• Choi Jaeyi

Classifications

• G09G2310/061

  for resetting or blanking · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G3/3266 Primary

  Details of drivers for scan electrodes · CPC title

• G09G2300/043

  Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver · CPC title

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title