Position-based rendering apparatus and method for multi-die/GPU graphics processing

Patent metadata

Field	Value
Publication number	US-10997771-B2
Application number	US-201816116158-A
Country	US
Kind code	B2
Filing date	Aug 29, 2018
Priority date	Aug 29, 2018
Publication date	May 4, 2021
Grant date	May 4, 2021

Abstract

Position-based rendering apparatus and method for multi-die/GPU graphics processing. For example, one embodiment of a method comprises: distributing a plurality of graphics draws to a plurality of graphics processors; performing position-only shading using vertex data associated with tiles of a first draw on a first graphics processor, the first graphics processor responsively generating visibility data for each of the tiles; distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors; limiting geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and wherein the rendered tiles are combined to generate a complete image frame.

First claim

What is claimed is:

1. A method comprising:
distributing a plurality of graphics draws to a plurality of graphics processors, wherein each of the plurality of graphics processors comprises a graphics pipeline to process a different subset of the plurality of graphics draws and each of the plurality of graphics draws comprises vertex data associated with one or more of a plurality of tiles;
performing, on a first graphics processor, position-only shading using vertex data associated with tiles of a first draw, the first graphics processor responsively generating visibility data for each of the tiles of the first draw;
distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors, wherein each of the different graphics processers is to receive a subset of the visibility data for a subset of the tiles on which the graphic processor is to perform geometry work, the subsets of visibility data to be distributed through point-to-point interconnect between the first graphics processor and each of the different graphics processors;
limiting the geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and
wherein the rendered tiles are combined to generate a complete image frame.

2. The method of claim 1 wherein each graphics processor is integrated on a separate semiconductor die.

3. The method of claim 1 wherein performing position-only shading comprises:
comparing primitives included in the vertex data for each tile to identify one or more primitives which are visible within the tile's region; and
identifying occluded primitives in the visibility data.

4. The method of claim 3 wherein limiting geometry work processing comprises performing geometry work only using those primitives which are visible.

5. The method of claim 3 further comprising:
rasterizing the subsets of tiles by each respective graphics processor to generate pixels for each tile of each subset of tiles.

6. The method of claim 5 further comprising:
performing pixel shading operations on each tile within each subset by each respective graphics processor to generate final pixels for each tile.

7. The method of claim 6 further comprising:
combining the final pixels for each tile within a frame buffer of at least one of the plurality of graphics processors.

8. The method of claim 1 further comprising:
performing position-only shading using vertex data associated with tiles of a second draw on a second graphics processor, the second graphics processor responsively generating second visibility data for each of the tiles of the second draw;
distributing the second visibility data for different subsets of the tiles of the second draw to different graphics processors;
limiting geometry work to be performed on each tile of the second draw by each graphics processor using the second visibility data, each graphics processor to responsively generate rendered tiles of the second draw; and
wherein the rendered tiles of the second draw are combined to generate a second image frame.

9. A graphics processing apparatus comprising:
a plurality of graphics processors to receive a plurality of graphics draws, wherein each of the plurality of graphics processors comprises a graphics pipeline to process a different subset of the plurality of graphics draws and each of the plurality of graphics draws comprises vertex data associated with one or more of a plurality of tiles;
an interconnect to couple the graphics processors;
a first graphics processor to perform position-only shading using vertex data associated with tiles of a first draw, the first graphics processor to responsively generate visibility data for each of the tiles of the first draw;
the first graphics processor to distribute subsets of the visibility data associated with different subsets of the tiles to different graphics processors of the plurality, wherein each of the different graphics processers is to receive a subset of the visibility data for a subset of the tiles on which the graphic processor is to perform geometry work, the subsets of visibility data to be distributed through point-to-point interconnect between the first graphics processor and each of the different graphics processors;
geometry shaders of each of the graphics processors to process primitives of a respective subset of tiles, the geometry shader to read the visibility data to limit the geometry work to be performed on each tile by each of the graphics processors,
wherein each graphics processor is to responsively generate rendered tiles; and
wherein the rendered tiles are to be combined to generate a complete image frame.

10. The graphics processing apparatus of claim 9 wherein each graphics processor is integrated on a separate semiconductor die.

11. The graphics processing apparatus of claim 9 wherein performing position-only shading comprises:
comparing primitives included in the vertex data for each tile to identify one or more primitives which are visible within the tile's region; and
identifying visible primitives in the visibility data.

12. The graphics processing apparatus of claim 11 wherein limiting geometry work processing comprises performing geometry work only using those primitives which are visible.

13. The graphics processing apparatus of claim 11 further comprising:
rasterizing the subsets of tiles by each respective graphics processor to generate pixels for each tile of each subset of tiles.

14. The graphics processing apparatus of claim 13 further comprising:
performing pixel shading operations on each tile within each subset by each respective graphics processor to generate final pixels for each tile.

15. The graphics processing apparatus of claim 14 further comprising:
combining the final pixels for each tile within a frame buffer of at least one of the plurality of graphics processors.

16. The graphics processing apparatus of claim 9 further comprising:
a second graphics processor to perform position-only shading using vertex data associated with tiles of a second draw, the second graphics processor to responsively generate second visibility data for each of the tiles of the second draw and to distribute the second visibility data for different subsets of the tiles of the second draw to different graphics processors;
the geometry shaders to process primitives of a respective subset of tiles of the second draw, the geometry shaders to read the second visibility data to limit geometry work to be performed,
wherein each graphics processor is to responsively generate rendered tiles of the second draw; and
wherein the rendered tiles of the second draw are combined to generate a second image frame.

17. A non-transitory machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform the operations of:
distributing a plurality of graphics draws to a plurality of graphics processors, wherein each of the plurality of graphics processors comprises a graphics pipeline to process a different subset of the plurality of graphics draws and each of the plurality of graphics draws comprises vertex data associated with one or more of a plurality of tiles;
performing, on a first graphics processor, position-only shading using vertex data associated with tiles of a first draw, the first graphics processor responsively generating visibility data for each of the tiles of the draw;
distributing subsets of the visibility data

Assignees

• Intel Corp

Inventors

• Schluessler Travis
• Waters Zack
• Apodaca Michael
• Johnston Daniel
• Surprise Jason
• Surti Prasoonkumar
• Maiyuran Subramaniam
• Doyle Peter
• Sharma Saurabh
• Shah Ankur
• Ramadoss Murali

Classifications

• G06T15/55

  Radiosity · CPC title

• G06T11/40

  Filling planar surfaces by adding surface attributes, e.g. adding colours or textures · CPC title

• G06T15/005 Primary

  General purpose rendering architectures · CPC title

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06T15/205

  Image-based rendering · CPC title