Conception of a 3D circuit comprising macros

Patent metadata

Field	Value
Publication number	US-10997346-B2
Application number	US-201916443509-A
Country	US
Kind code	B2
Filing date	Jun 17, 2019
Priority date	Jun 18, 2018
Publication date	May 4, 2021
Grant date	May 4, 2021

Abstract

A method of 3D circuit conception comprising: providing, to a circuit conception tool, circuit design files representing a 3D circuit design including one or more first circuit elements attributed to a first tier of the 3D circuit and one or more second circuit elements attributed to a second tier of the 3D circuit; modifying, by the circuit conception tool, a property of the one or more first and/or second circuit elements to permit any of the second circuit elements to superpose, or be superposed by, any of the first circuit elements; and performing, by the circuit conception tool, placement and routing of the 3D circuit design based on a 2D circuit representation, interconnection nodes of the one or more second circuit elements being defined in one or more interconnection levels of the 2D circuit representation.

First claim

The invention claimed is:

1. A method of 3D circuit conception comprising:
providing, to a circuit conception tool, circuit design files representing a 3D circuit design including one or more first circuit elements attributed to a first tier of the 3D circuit and one or more second circuit elements attributed to a second tier of the 3D circuit;
modifying, by the circuit conception tool, a property of the one or more first and/or second circuit elements to permit any of the second circuit elements to superpose, or be superposed by, any of the first circuit elements;
performing, by the circuit conception tool, placement and routing of the 3D circuit design to generate a 3D circuit layout of the 3D circuit design, wherein the placement and routing is based on a 2D circuit representation, interconnection nodes of the one or more second circuit elements being defined in one or more interconnection levels of the 2D circuit representation, the placement comprising placing one or more of the second circuit elements to at least partially superpose one or more of the first circuit elements and the routing comprising routing connections between the one or more first circuit elements and the one or more second circuit elements via the interconnection nodes defined in the one or more interconnection levels; and
generating a final 3D circuit layout by extracting, from the 3D circuit layout, a first circuit layout of the first tier comprising the one or more first circuit elements and a second circuit layout of the second tier comprising the one or more second circuit elements, wherein
interconnection nodes of the one or more first circuit elements are each defined in one of a first set of metal levels of the 2D circuit representation corresponding to metal levels of the first tier; and
interconnection nodes of the one or more second circuit elements are each defined in one of a second set of metal levels of the 2D circuit representation corresponding to metal levels of the second tier so that routing between the interconnection nodes of the one or more first circuit elements and the interconnection nodes of the one or more second circuit elements can be performed.

2. The method of claim 1 , further comprising:
transmitting the final 3D circuit layout of the 3D circuit design to a manufacturing site for fabrication.

3. The method of claim 1 , further comprising fabricating a 3D circuit design based on the final 3D circuit layout.

4. The method of claim 1 , further comprising, after performing placement and routing, performing by the circuit conception tool, post-routing optimization of the placement of at least one of the first or second circuit elements.

5. The method of claim 1 , wherein modifying the property of the one or more first and/or second circuit elements to permit any of them to superpose, or be superposed by, any of the first circuit elements comprises defining an overlap layer in each of the one or more second circuit elements, the overlap layer defining a region of each second circuit element that can be superposed by other circuits.

6. The method of claim 1 , wherein modifying the property of the one or more first and/or second circuit elements to permit any of them to superpose, or be superposed by, any of the first circuit elements comprises defining each of the second circuit elements as a cover class.

7. The method of claim 1 , further comprising, prior to providing the circuit design files to the circuit conception tool, attributing, by the circuit conception tool, the one or more first circuit elements to the first tier of the 3D circuit and one or more second circuit elements to the second tier of the 3D circuit.

8. The method of claim 1 , wherein the interconnection nodes of the one or more second circuit elements are 3D interconnection PADs, and the one or more interconnection levels is a hybrid bonding layer.

9. The method of claim 1 , wherein the at least one first circuit element comprises one or more macros, and the at least one second circuit element comprises one or more logic cells.

10. The method of claim 9 , wherein the one or more macros are defined in the circuit design files as being encapsulated in a top level in which the 3D interconnection pads are present.

11. The method of claim 9 , wherein the 3D circuit layout comprises one or more tiers comprising only said macros.

12. The method of claim 9 , further comprising, prior to performing the placement and routing, a synthesis operation during which a functional definition of a logic circuit of the 3D circuit design is translated into a netlist defining said one or more logic cells.

13. The method of claim 12 , wherein said synthesis operation is based on a pre-placement of the one or more macros in a 3D floorplan.

14. A circuit conception system comprising:
one or more processors; and
one or more memories storing software instructions that cause the one or more processors to implement the method of claim 1 .

15. A non-transitory storage medium storing software instructions that cause the method of claim 1 to be implemented when the instructions are executed by one or more processors.

Assignees

• Commissariat Energie Atomique

Inventors

• Thuries Sébastien
• Billoint Olivier
• Lattard Didier
• Vivet Pascal

Classifications

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F2119/18

  Manufacturability analysis or optimisation for manufacturability · CPC title

• G06F30/327

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title