Method of encoding data

Patent metadata

Field	Value
Publication number	US-10997016-B2
Application number	US-201916506066-A
Country	US
Kind code	B2
Filing date	Jul 9, 2019
Priority date	Jul 15, 2013
Publication date	May 4, 2021
Grant date	May 4, 2021

Abstract

Techniques for encoding data are described herein. The method includes receiving a block payload at a physical layer to be transmitted via a data bus. The method includes establishing a block header comprising an arrangement of bits, the block header defining two block header types, wherein a hamming distance between block header types is at least four.

First claim

What is claimed is:

1. An electronic device interface, comprising:
an encoder to establish a block header comprising an arrangement of bits, the block header defining two block header types, wherein a hamming distance between the two block header types is four; and
a transmitter to transmit the block header followed by a block payload, wherein a bit rate clock is to enable correction of errors in the block header without re-transmission of the block header and the block payload.

2. The electronic device interface of claim 1 , wherein the block header and block payload are transmitted as 128b/132b line encoded data.

3. The electronic device interface of claim 1 , wherein a scrambler is bypassed for the bits of the block header.

4. The electronic device interface of claim 1 , wherein the block payload comprises 128 bits and the block header comprises four bits.

5. The electronic device interface of claim 1 , wherein a first block header type is a data block header type and a second block header type is a control block header type.

6. The electronic device interface of claim 5 , wherein the data block header type indicates a data block payload is to follow and the control block header type indicates that a control message payload is to follow.

7. The electronic device interface of claim 1 , wherein a bit rate clock is embedded in a data stream that comprises the block header and the block payload.

8. The electronic device interface of claim 1 , wherein in response to a configuration of a single bit, a scrambler is to be bypassed.

9. A method of decoding data, comprising:
receiving 128b/132b line encoded data comprising a four-bit block header followed by a 128 bit block payload;
identifying a block header comprising an arrangement of bits, the block header defining content of a block payload using two block header types comprising a data block header type and a control block header type; and
wherein a hamming distance between the two block header types is four.

10. The method of claim 9 , wherein the data block header type indicates a data block payload is to follow and the control block header type indicates that a control message payload is to follow.

11. The method of claim 9 , comprising correcting a single bit error.

12. The method of claim 9 , comprising detecting a two bit error.

13. The method of claim 9 , wherein the four bit block header is not scrambled.

14. The method of claim 9 , comprising descrambling the block payload based in part on a reference clock.

15. The method of claim 9 , comprising deriving a recovered symbol clock from a bit rate clock embedded in the line encoded data.

16. The method of claim 9 , wherein the block payload is transmitted at a DisplayPort (DP) interface.

17. A method of encoding data, comprising:
establishing a block header comprising an arrangement of four bits that enables detection and correction of single bit errors within the block header, the block header defining two block header types; and
transmitting the block header followed by a block payload comprising 128 bits of block data, wherein a hamming distance between the two block header types is to enable correction of single bit errors in the block header without re-transmission of the block header and the block payload.

18. The method of claim 17 , comprising embedding a bit rate clock in a data stream that comprises the block header and the block payload.

19. The method of claim 17 , comprising bypassing scrambling of the bits of the block header.

20. The method of claim 17 , comprising scrambling of the bits of the block payload.

21. The method of claim 17 , wherein the block header and the block payload are transmitted at a DisplayPort (DP) interface.

Assignees

• Intel Corp

Inventors

• Chen Huimin
• Martwick Andrew
• Heck Howard
• Dunstan Robert
• Bell Dennis
• Ismail Abdul

Classifications

• G06F11/10 Primary

  Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's · CPC title

• H03M5/06

  Code representation, e.g. transition, for a given bit cell depending only on the information in that bit cell · CPC title

• H03M5/12

  Biphase level code, e.g. split phase code, Manchester code; Biphase space or mark code, e.g. double frequency code · CPC title