Regulators with offset voltage cancellation

Patent metadata

Field	Value
Publication number	US-10996694-B2
Application number	US-201916448162-A
Country	US
Kind code	B2
Filing date	Jun 21, 2019
Priority date	Jun 21, 2019
Publication date	May 4, 2021
Grant date	May 4, 2021

Abstract

A regulator includes an operational amplifier, a programmable offset voltage, and a circuit. The operational amplifier includes a non-inverting input, an inverting input, and an output. The programmable offset voltage is configured to cancel a built-in offset voltage of the regulator based on a code. The circuit is configured to set the code based on a sensed built-in offset voltage of the regulator in response to an offset cancellation calibration mode enable signal.

First claim

What is claimed is:

1. A regulator comprising:
an operational amplifier comprising a non-inverting input, an inverting input, and an output;
a programmable offset voltage configured to cancel a built-in offset voltage of the regulator based on a code; and
a circuit configured to set the code based on a sensed built-in offset voltage of the regulator in response to an offset cancellation calibration mode enable signal,
wherein the programmable offset voltage is coupled between the non-inverting input and the inverting input during both an operating mode and an offset cancellation calibration mode of the regulator.

2. The regulator of claim 1 , wherein the code comprises four bits.

3. The regulator of claim 1 , wherein a polarity and a magnitude of the built-in offset voltage is random.

4. A regulator comprising:
an operational amplifier comprising a non-inverting input, an inverting input, and an output;
a programmable offset voltage configured to cancel a built-in offset voltage of the regulator based on a code;
a circuit configured to set the code based on a sensed built-in offset voltage of the regulator in response to an offset cancellation calibration mode enable signal;
a first switch to directly connect the non-inverting input to the inverting input of the operational amplifier in response to the offset cancellation calibration mode enable signal; and
a second switch to disconnect the inverting input of the operational amplifier from a feedback path of the regulator in response to the offset cancellation calibration mode enable signal.

5. The regulator of claim 4 , further comprising:
a first transistor to supply a regulated voltage to a load;
a third switch to connect a voltage supply to a gate of the first transistor in response to the offset cancellation calibration mode enable signal; and
a fourth switch to disconnect the output of the operational amplifier from the gate of the first transistor in response to the offset cancellation calibration mode enable signal.

6. The regulator of claim 4 , further comprising:
a first transistor having a gate electrically coupled to the output of the operational amplifier, the first transistor to supply a regulated voltage to a load;
a second transistor having a gate electrically coupled to the output of the operational amplifier, the second transistor to supply a voltage to the circuit;
a third switch to disable the first transistor in response to the offset cancellation calibration mode enable signal; and
a fourth switch to enable the second transistor in response to the offset cancellation calibration mode enable signal.

7. The regulator of claim 4 , further comprising:
a first transistor electrically coupled to the output of the operational amplifier to supply a regulated voltage to a load, the first transistor having a first width; and
a second transistor electrically coupled to the output of the operational amplifier to supply a voltage to the circuit, the second transistor having a second width less than 20 percent of the first width.

8. The regulator of claim 7 , wherein the circuit comprises:
a detector electrically coupled to the second transistor to compare the voltage supplied by the second transistor to a target voltage; and
a state machine to set the code based on the comparison.

9. A regulator comprising:
an operational amplifier comprising a non-inverting input, an inverting input, and a first output;
a reference voltage node to provide a reference voltage to the non-inverting input of the operational amplifier;
a regulated voltage node to supply a regulated voltage to a load based on the reference voltage; and
a programmable offset voltage controlled to cancel a built-in offset voltage between the reference voltage and the regulated voltage,
wherein the programmable offset voltage is coupled between the non-inverting input and the inverting input during both an operating mode and an offset cancellation calibration mode of the regulator.

10. A regulator comprising:
an operational amplifier comprising a non-inverting input, an inverting input, and a first output;
a reference voltage node to provide a reference voltage to the non-inverting input of the operational amplifier;
a regulated voltage node to supply a regulated voltage to a load based on the reference voltage;
a programmable offset voltage controlled to cancel a built-in offset voltage between the reference voltage and the regulated voltage;
a first transistor electrically coupled to the first output of the operational amplifier and the regulated voltage node;
a first current source electrically coupled to the regulated voltage node; and
a controller configured to connect the regulated voltage node to the inverting input of the operational amplifier during an operating mode of the regulator and to disconnect the regulated voltage node from the inverting input of the operating amplifier during an offset cancellation calibration mode of the regulator.

11. A regulator comprising:
an operational amplifier comprising a non-inverting input, an inverting input, and a first output;
a reference voltage node to provide a reference voltage to the non-inverting input of the operational amplifier;
a regulated voltage node to supply a regulated voltage to a load based on the reference voltage;
a programmable offset voltage controlled to cancel a built-in offset voltage between the reference voltage and the regulated voltage;
a first transistor electrically coupled to the first output of the operational amplifier and the regulated voltage node;
a first current source electrically coupled to the regulated voltage node;
a controller configured to connect the regulated voltage node to the inverting input of the operational amplifier during an operating mode of the regulator and to disconnect the regulated voltage node from the inverting input of the operating amplifier during an offset cancellation calibration mode of the regulator;
an offset voltage sensing node;
a second transistor electrically coupled to the first output of the operational amplifier and the offset voltage sensing node; and
a second current source electrically coupled to the offset voltage sensing node,
wherein the controller is configured to disconnect the non-inverting input from the inverting input of the operational amplifier during the operating mode of the regulator and to connect the non-inverting input to the inverting input of the operational amplifier during the offset cancellation calibration mode of the regulator.

12. The regulator of claim 11 , further comprising:
a detector electrically coupled to the offset voltage sensing node, the detector configured to output a bit indicating whether a voltage on the offset voltage sensing node is above or below a target voltage.

13. The regulator of claim 12 , further comprising:
a state machine electrically coupled to the detector, the state machine configured to generate a code to control the programmable offset voltage based on the bit output by the detector.

14. The regulator of claim 13 , further comprising:
an oscillator to generate a first compare clock signal, a second compare clock signal, and an offset cancellation mode clock signal in response to an offset cancellation calibration mode enable signal;
a first register to store a first bit output from the detector in response to the first compare clock signal; and
a second register to store a second bit output from the detector in response to the second compare clock signal,
wherein, in response to the offset cancellation mode clock signal, a counter of the state machine is increment

Assignees

• Micron Technology Inc

Inventors

• Nam Ki-Jun
• Porter John David

Classifications

• G05F1/575

  characterised by the feedback circuit · CPC title

• H03F3/45771

  using switching means · CPC title

• H03F3/45995

  using switching means · CPC title

• H02M1/0067

  Converter structures employing plural converter units, other than for parallel operation of the units on a single load · CPC title

• G05F1/565 Primary

  sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor (G05F1/563 takes precedence) · CPC title