Low-complexity beamforming for a multi-line communication system

Patent metadata

Field	Value
Publication number	US-10992341-B2
Application number	US-201916442952-A
Country	US
Kind code	B2
Filing date	Jun 17, 2019
Priority date	Jun 17, 2019
Publication date	Apr 27, 2021
Grant date	Apr 27, 2021

Abstract

A multi-line digital transceiver configured to use low-complexity beamforming on at least some tones to boost effective SNR values for selected subscriber lines. In an example embodiment, the beamforming coefficients can be restricted to one-bit values or two-bit values, e.g., such that the corresponding beamforming computations can be implemented using only sign changes, swaps of the real and imaginary parts, and/or zeroing of some values, and without invoking any full-precision hardware multiplication operations. At least some embodiments can be run on a significantly simpler and/or less powerful vectoring engine than conventional beamforming solutions while still being able to provide nearly optimal beamforming SNR gains. In some embodiments, additional scaling by powers of two may be applied to at least some signals contributing to the beamforming, e.g., to satisfy power constraints for some or all of the subscriber lines.

First claim

What is claimed is:

1. An apparatus comprising a data transmitter that comprises an analog front end connectable to proximal ends of a plurality of subscriber lines and a digital signal processor configured to drive the analog front end to cause a plurality of output signals to be transmitted on the subscriber lines using frequency-division multiplexing;
wherein the digital signal processor comprises a vector processor configured to:
for a first tone, generate a plurality of first precoded data signals by applying a plurality of weighting factors to a value being communicated to a data receiver at a distal end of a selected one of the subscriber lines; and
drive the analog front end to apply each of the first precoded data signals to a respective one of the subscriber lines;

wherein the first precoded data signals that are applied to the subscriber lines other than the selected one of the subscriber lines are coupled to the selected one of the subscriber lines by way of interline crosstalk on the first tone;
wherein the weighting factors are selected such as to cause constructive interference of the first precoded data signals received by the data receiver, each of the weighting factors being represented by a one-bit value, a two-bit value, or a three-bit value; and
wherein the signal processor further comprises a plurality of symbol encoders and a data selector configured to select for a given symbol period a single symbol value from a plurality of symbol values generated by the symbol encoders and apply said single symbol value to the vector processor, said single symbol value being the value communicated to the data receiver in the given symbol period.

2. The apparatus of claim 1 , wherein each of the weighting factors is selected from a set consisting of 1 and −1.

3. The apparatus of claim 1 , wherein each of the weighting factors is selected from a set consisting of 1, −1, j, and −j.

4. The apparatus of claim 1 , wherein each of the weighting factors is selected from a set consisting of 0, 1, −1, j, and −j.

5. The apparatus of claim 1 , wherein each of the weighting factors is selected from a set consisting of 0, 1, and −1.

6. The apparatus of claim 1 , wherein the vector processor is configured to apply any of the weighting factors to the value without performing a hardware multiplication operation.

7. The apparatus of claim 1 , wherein the vector processor is configured to apply any of the weighting factors to the value using one or more operations from a set comprising:
a sign-bit change;
a swap of real and imaginary parts of a complex value; and
setting a value to zero.

8. The apparatus of claim 1 , wherein the vector processor is further configured to generate, for a second tone, a plurality of second precoded data signals by applying a vector-to-vector transformation to a plurality of values, each of the plurality of values being communicated to a respective data receiver at a distal end of a respective one of the subscriber lines, the vector-to-vector transformation being configured to cause effects of interline crosstalk on the second tone to be substantially mitigated at the respective data receiver.

9. The apparatus of claim 8 , wherein the data transmitter is configured to transmit data on a plurality of first tones and a plurality of second tones.

10. The apparatus of claim 9 , wherein each of the first tones has a higher frequency than any of the second tones.

11. The apparatus of claim 1 , further comprising an additional processor in communication with the digital signal processor by way of an optical link, the additional processor being configured to perform some of computations that enable the digital signal processor to drive the analog front end and to cause the plurality of output signals to be transmitted on the subscriber lines.

12. The apparatus of claim 11 , wherein the additional processor and the digital signal processor are configured to generate, for a second tone, a plurality of second precoded data signals by applying a vector-to-vector transformation to a plurality of values, each of the plurality of values being communicated to a respective data receiver at a distal end of a respective one of the subscriber lines, the vector-to-vector transformation being configured to cause effects of interline crosstalk on the second tone to be substantially mitigated at the respective data receivers.

13. The apparatus of claim 1 , further comprising an electronic controller configured to control flows of data through the digital signal processor such that, during a given symbol period, the first tone carries data corresponding to a single subscriber.

14. The apparatus of claim 1 , wherein the digital signal processor further comprises a plurality of encapsulation modules, a plurality of framers, a plurality of symbol encoders, and a plurality of modulators connected to the vector processor.

15. An apparatus comprising a data receiver that comprises an analog front end and a digital signal processor configured to process digital samples corresponding to a plurality of input signals received by the analog front end at input ports connectable to proximal ends of a corresponding plurality of subscriber lines, the input signals being received in response to data signals applied to distal ends of the subscriber lines, the data signals having been encoded with data using frequency-division multiplexing;
wherein the digital signal processor comprises a vector processor configured to generate, for a first tone, an output value by computing a weighted sum of input values, each of the input values corresponding to the first tone of a respective one of the input signals, the weighted sum being computed using a plurality of weighting factors, the input signals on the first tone thereof being received in response to a single one of the data signals, the single one of the data signals having been coupled to multiple ones of the subscriber lines by way of interline crosstalk on the first tone;
wherein the weighting factors are selected such as to cause addends of the weighted sum to add constructively, each of the weighting factors being represented by a one-bit value, a two-bit value, or a three-bit value; and
wherein the signal processor further comprises a plurality of symbol decoders and a data selector configured to apply the weighted sum to a selected one of the symbol decoders in a given symbol period, the weighted sum being an only value for the first tone passed by the data selector from the vector processor to the plurality of symbol decoders in the given symbol period.

16. The apparatus of claim 15 , wherein each of the weighting factors is selected from a set consisting of 1 and −1.

17. The apparatus of claim 15 , wherein each of the weighting factors is selected from a set consisting of 1, 0, and −1.

18. The apparatus of claim 15 , wherein each of the weighting factors is selected from a set consisting of 1, −1, j, and −j.

19. The apparatus of claim 15 , wherein each of the weighting factors is selected from a set consisting of 1, 0, −1, j, and −j.

20. The apparatus of claim 15 , wherein the vector processor is configured to apply any of the weighting factors to the input values without performing a hardware multiplication operation.

21. The apparatus of claim 15 , wherein the vector processor is configured to apply any of the weighting factors to the input values using one or more operations from a set comprising:
a sign-bit change;
a swap of real and imaginary parts of a

Assignees

• Nokia Solutions & Networks Oy

Inventors

• Tsiaflakis Paschalis
• Maes Jochen
• Coomans Werner
• Nuzman Carl

Classifications

• H04J1/00

  Frequency-division multiplex systems (H04J14/00 takes precedence) · CPC title

• H04B3/32 Primary

  Reducing cross-talk, e.g. by compensating · CPC title

• H04B3/487

  Testing crosstalk effects · CPC title

• H04J11/0033

  by pre-cancellation of known interference, e.g. using a matched filter, dirty paper coder or Thomlinson-Harashima precoder (correlative coding in synchronous or start-stop systems H04L25/497) · CPC title

• H04B3/542

  the information being in digital form · CPC title