Architectures enabling back contact bottom electrodes for semiconductor devices

US10991836B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10991836-B2
Application numberUS-201716085422-A
CountryUS
Kind codeB2
Filing dateMar 15, 2017
Priority dateMar 15, 2016
Publication dateApr 27, 2021
Grant dateApr 27, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor device and method for fabricating same is disclosed. Embodiments are directed to a semiconductor device and fabrication of same which include a polycrystalline or amorphous substrate. An electrically conductive Ion Beam-Assisted Deposition (IBAD) template layer is positioned above the substrate. At least one electrically conductive hetero-epitaxial buffer layer is positioned above the IBAD template layer. The at least one buffer layer has a resistivity of less than 100 μΩcm. The semiconductor device and method foster the use of bottom electrodes thereby avoiding complex and expensive lithography processes.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device comprising: a polycrystalline or amorphous substrate; an electrically conductive Ion Beam-Assisted Deposition (IBAD) template layer positioned above the substrate; and at least one electrically conductive hetero-epitaxial buffer layer positioned above the IBAD template layer, wherein the at least one buffer layer has a resistivity of less than 100 μΩcm, and wherein the at least one buffer layer comprises a fluorite structure that has a (004) out-of-plane orientation; wherein the substrate comprises metal and functions as a back contact bottom electrode, or the semiconductor device further comprises a back contact bottom electrode positioned below the substrate. 2. The semiconductor device of claim 1 , wherein the IBAD template layer comprises Titanium Nitride (TiN). 3. The semiconductor device of claim 1 , wherein the at least one buffer layer does not comprise an oxide. 4. The semiconductor device of claim 1 , wherein the fluorite structure comprises Nickel Silicide (NiSi 2 ). 5. The semiconductor device of claim 1 , further comprising an electrically conductive amorphous layer positioned between the substrate and the IBAD template layer. 6. The semiconductor device of claim 5 , wherein the amorphous layer comprises Titanium Nitride (TiN) or Tantalum-Nickel (Ta—Ni). 7. The semiconductor device of claim 1 , further comprising an epitaxial Si film or an epitaxial Ge film positioned above the at least one buffer layer. 8. The semiconductor device of claim 1 , further comprising an epitaxial Si film positioned above the at least one buffer layer, and p-doped and n-doped silicon positioned above the epitaxial Si film, thereby forming a solar cell device or flexible electronics device. 9. The semiconductor device of claim 1 , further comprising an epitaxial Ge film positioned above the at least one buffer layer, and epitaxial GaAs film positioned on the epitaxial Ge film, and epitaxial p-doped and epitaxial n-doped GaAs layers positioned on the epitaxial GaAs film, thereby forming a solar cell device. 10. The semiconductor device of claim 1 , wherein the substrate comprises metal. 11. The semiconductor device of claim 1 , wherein the substrate comprises metal and functions as a bottom electrode. 12. The semiconductor device of claim 1 , wherein the substrate comprises glass. 13. The semiconductor device of claim 1 , further comprising a bottom electrode positioned below and attached to the substrate. 14. The semiconductor device of claim 1 , wherein the substrate is Hastelloy C-276 or Stainless Steel or Ni—W or Ni—Cr or Inconel or copper or a combination thereof. 15. The semiconductor device of claim 1 , further comprising a homo-epitaxial layer positioned between the IBAD template layer and the at least one buffer layer. 16. The semiconductor device of claim 15 , wherein the homo-epitaxial layer comprises TiN. 17. The semiconductor device of claim 4 , wherein the fluorite structure has a resistivity of 5 μΩcm.

Assignees

Inventors

Classifications

  • the metallic or insulating substrates being flexible · CPC title

  • the films including only Group IV materials · CPC title

  • the coatings being antireflective or having enhancing optical properties · CPC title

  • for photovoltaic cells · CPC title

  • comprising only Group III-V materials, e.g. GaAs · CPC title

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What does patent US10991836B2 cover?
A semiconductor device and method for fabricating same is disclosed. Embodiments are directed to a semiconductor device and fabrication of same which include a polycrystalline or amorphous substrate. An electrically conductive Ion Beam-Assisted Deposition (IBAD) template layer is positioned above the substrate. At least one electrically conductive hetero-epitaxial buffer layer is positioned abo…
Who is the assignee on this patent?
Univ Houston System
What technology area does this patent fall under?
Primary CPC classification H10F77/169. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 27 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).