Memory-in-pixel circuit, driving method thereof, array substrate, and display apparatus

Patent metadata

Field	Value
Publication number	US-10991289-B2
Application number	US-201816346962-A
Country	US
Kind code	B2
Filing date	Sep 27, 2018
Priority date	Apr 26, 2018
Publication date	Apr 27, 2021
Grant date	Apr 27, 2021

Abstract

The present disclosure is related to a memory-in-pixel circuit. The memory-in-pixel circuit comprises a switch sub-circuit, and a data input sub-circuit. The data input sub-circuit comprises a first floating gate transistor and a second floating gate transistor. The data input sub-circuit is configured to transmit a data signal from one of a plurality of data lines to a pixel electrode under control of the switch sub-circuit.

First claim

What is claimed is:

1. A memory-in-pixel circuit, comprising,
a switch sub-circuit, and
a data input sub-circuit, the data input sub-circuit comprising a first floating gate transistor and a second floating gate transistor,
wherein the data input sub-circuit is configured to transmit a data signal from one of a plurality of data lines to a pixel electrode under control of the switch sub-circuit,
a threshold voltage of each of the first floating gate transistor and the second floating gate transistor is configured to shift negatively when a negative gate voltage is applied and shift positively when a positive gate voltage is applied, and
the first floating gate transistor and the second floating gate transistor have a threshold voltage, a positive threshold voltage shift of the threshold voltage (V th− ), and a negative voltage shift of the threshold voltage (V th+ ); a first data signal is transmitted through the first floating gate transistor, and a second data signal is transmitted through the second floating gate transistor; V w+ is a high voltage of the first data signal in a data remain stage, V w− is a low voltage of the first data signal in the data remain stage; V B+ is a high voltage of the second data signal in the data remain stage, V B− is a low voltage of the second data signal in the data remain stage; V TL1 is a control voltage of the first floating gate in the data remain stage, and V TL2 is a control voltage of the second floating gate in the data remain stage; the first floating gate transistor and the second floating gate transistor maintain a stable status in the data remain stage with V TL1 and V TL2 in ranges limited by V th+ , V th− , V B+ , V B− , V w+ , and V W− .

2. The memory-in-pixel circuit according to claim 1 , wherein the switch sub-circuit comprises a first switch transistor and a second switch transistor;
a control electrode of the first switch transistor is coupled to a gate line, a first electrode of the first switch transistor is coupled to a first control-signal terminal, a second electrode of the first switch transistor is coupled to a control electrode of the first floating gate transistor; and
a control electrode of the second switch transistor is coupled to the gate line, a first electrode of the second switch transistor is coupled to a second control-signal terminal, a second electrode of the second switch transistor is coupled to a control electrode of the second floating gate transistor.

3. The memory-in-pixel circuit according to claim 2 , wherein the switch sub-circuit is configured to transmit a first control-signal from the first control-signal terminal and a second control-signal from the second control-signal terminal to the first floating gate transistor and the second floating gate transistor respectively under control of a gate signal of the gate line.

4. The memory-in-pixel circuit according to claim 1 , wherein,
the plurality of data lines comprises a first data line and a second data line;
a first electrode of the first floating gate transistor is coupled to the first data line, a second electrode of the first floating gate transistor is coupled to the pixel electrode; and
a first electrode of the second floating gate transistor is coupled to the second data line, a second electrode of the second floating gate transistor is coupled to the pixel electrode.

5. The memory-in-pixel circuit according to claim 1 , wherein the first floating gate transistor and the second floating gate transistor are n-type transistors, and the first switch transistor and the second switch transistor are n-type transistors.

6. The memory-in-pixel circuit according to claim 4 , further comprising, a storage sub-circuit,
wherein the storage sub-circuit is configured to sustain potentials of the control electrode of the first floating gate transistor and the control electrode of the second floating gate transistor.

7. The memory-in-pixel circuit according to claim 4 , further comprising,
a storage sub-circuit,
wherein the storage sub-circuit is configured to sustain a potential of the control electrode of the first floating gate transistor at a potential of the first control-signal and a potential of the control electrode of the second floating gate transistor at a potential of the second control-signal when the switch sub-circuit is turned on.

8. The memory-in-pixel circuit according to claim 6 , wherein
the storage sub-circuit comprises a capacitor, a first electrode of the capacitor is coupled to the control electrode of the first floating gate transistor, and a second electrode of the capacitor is coupled to the control electrode of the second floating gate transistor.

9. The memory-in-pixel circuit according to claim 6 , wherein
the storage sub-circuit comprises a first capacitor and a second capacitor;
a first electrode of the first capacitor is coupled to the control electrode of the first floating gate transistor, a second electrode of the first capacitor is coupled to a common electrode:
a first electrode of the second capacitor is coupled to the control electrode of the second floating gate transistor, and a second electrode of the second capacitor is coupled to a common electrode.

10. The memory-in-pixel circuit according to claim 8 , further comprising a third capacitor;
wherein a first electrode of the third capacitor is coupled to the pixel electrode, a second electrode of the third capacitor is coupled to a common electrode; and the third capacitor is configured to sustain a potential of the pixel electrode.

11. The memory-in-pixel circuit according to claim 10 , wherein a dielectric of the third capacitor is insulating material.

12. An array substrate, comprising a plurality of pixel units, wherein
at least one of the plurality of the pixel units comprises the memory-in-pixel circuit according to claim 1 .

13. The array substrate according to claim 12 , comprising a plurality of gate lines, wherein the plurality of pixel units are arranged in an array, and switch sub-circuits arranged in a same row are coupled to a same gate line.

14. A display apparatus, comprising the array substrate according to claim 12 .

15. A driving method of a memory-in-pixel circuit, wherein,
the memory-in-pixel circuit comprises a switch sub-circuit and a data input sub-circuit, the data input sub-circuit comprising a first floating gate transistor and a second floating gate transistor; the driving method comprising:
transmitting control signals from a plurality of control-signal terminals to the data input sub-circuit through the switch sub-circuit under control of a gate signal of a gate line; and
transmitting a data signal from one of a plurality of data lines to a pixel electrode through the data input sub-circuit,
wherein only one of the control signals from the plurality of control-signal terminals is a negative voltage,
a threshold voltage of each of the first floating gate transistor and the second floating gate transistor is configured to shift negatively when a negative gate voltage is applied and shift positively when a positive gate voltage is applied, and
the first floating gate transistor and the second floating gate transistor have a threshold voltage, a positive threshold voltage shift of the threshold voltage (V th− ), and a negative voltage shift of the threshold voltage (V th+ ); a first data signal is transmitted through the first floating gate transistor, and a second data signal is transmitted through the second floating gate transistor; V w+ is a high voltage of the first data signal in a data remain stage. V w− is a low voltage of the

Assignees

• Boe Technology Group Co Ltd

Inventors

• Shang Guangliang
• Han Chengyou
• Han Mingfu
• Yuan Lijun
• Yao Xing
• Zheng Haoliang

Classifications

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G3/3688

  suitable for active matrices only · CPC title

• G09G3/3225

  using an active matrix · CPC title

• G09G3/3611 Primary

  Control of matrices with row and column drivers · CPC title

• G09G2300/0439

  Pixel structures · CPC title