System, method and computer-accessible medium for stripped-functionality logic locking

Patent metadata

Field	Value
Publication number	US-10990580-B2
Application number	US-201816170378-A
Country	US
Kind code	B2
Filing date	Oct 25, 2018
Priority date	Oct 25, 2017
Publication date	Apr 27, 2021
Grant date	Apr 27, 2021

Abstract

An exemplary system, method and computer-accessible medium for modifying a design of an integrated circuit(s) (ICs), which can include, for example, modifying a logic gate(s) in the design for a protected input pattern(s), and providing a restoration unit(s) into the design, where the restoration unit(s) can be configured to (i) produce an error-free output(s) when a correct secret key can be applied to the restoration unit(s), and (ii) produce an erroneous output(s) when an incorrect key can be applied to the restoration unit(s); and ensure that the modified design along with the restoration unit produces at least one erroneous output with respect to the original design for only a pre-determined constant number of incorrect keys based on at least one input pattern.

First claim

What is claimed is:

1. A non-transitory computer-accessible medium having stored thereon computer-executable instructions for modifying a design of at least one integrated circuit (IC), wherein, when a computer arrangement executes the instructions, the computer arrangement is configured to perform procedures comprising:
modifying at least one logic gate in the design for at least one protected input pattern, wherein the at least one protected input pattern is an input pattern for which the modified design produces a different output than an original design;
providing at least one restoration unit into the design, wherein the at least one restoration unit is configured to (i) produce at least one error-free output when a correct secret key is applied to the at least one restoration unit, and (ii) produce at least one erroneous output when an incorrect key is applied to the at least one restoration unit; and
performing at least one of:
(i) determining that the design and the at least one restoration unit produce at least one erroneous output with respect an original design for only a pre-determined constant number of incorrect keys based on at least one input pattern, or
(ii) modifying the at least one logic gate based on a security-aware synthesis procedure which is configured to reduce at least one design metric while ensuring that k-−log 2 c is greater than a target security level, and wherein k is a key size and c is a number of cube.

2. The computer-accessible medium of claim 1 , wherein the at least one restoration unit includes at least one Hamming Distance checker configured to check a Hamming Distance between the at least one input pattern and at least one key.

3. The computer-accessible medium of claim 2 , wherein the computer arrangement is configured to use the at least one Hamming Distance checker to protect input patterns that are of a pre-determined Hamming Distance away from at least one correct key.

4. The computer-accessible medium of claim 3 , wherein the at least one correct key is stored in a tamper-proof memory.

5. The computer-accessible medium of claim 1 , wherein the at least one restoration unit includes a tamper-proof content-addressable look-up table.

6. The computer-accessible medium of claim 5 , wherein the computer arrangement is further configured to use the tamper-proof content-addressable look-up table to protect input patterns that are included in a plurality of input cubes stored in the tamper-proof content-addressable look-up table.

7. The computer-accessible medium of claim 6 , wherein the computer arrangement is further configured to determine the input cubes based on set of protected input patterns using at least one of (i) a cube compression procedure, or (ii) a cube bit selection procedure.

8. The computer-accessible medium of claim 6 , wherein each of the input cubes has a predetermined number of bits.

9. The computer-accessible medium of claim 6 , wherein each of the input cubes includes a secret key loaded on to the at least one integrated circuit.

10. The computer-accessible medium of claim 6 , wherein the input cubes are associated with at least one flip vector.

11. The computer-accessible medium of claim 10 , wherein the at least one flip vector includes information regarding which outputs of the at least one integrated circuit are to be flipped based on each of the input cubes.

12. The computer-accessible medium of claim 11 , wherein the computer arrangement is further configured to store the at least one flip vector in the tamper-proof content-addressable look-up table.

13. The computer-accessible medium of claim 6 , wherein the computer arrangement is further configured to compress the input cubes prior to being stored in the tamper-proof content-addressable look-up table.

14. The computer-accessible medium of claim 13 , wherein the computer arrangement is configured to compress the input cubes by merging compatible input cubes.

15. The computer-accessible medium of claim 1 , wherein the at least one restoration unit includes a plurality of XOR gates and at least one adder.

16. The computer-accessible medium of claim 1 , wherein the at least one design metric includes at least one of (i) a power, (ii) an area, or (iii) a delay.

17. A method for modifying a design of at least one integrated circuit (IC), comprising:
modifying at least one logic gate in the design for at least one protected input pattern, wherein the at least one protected input pattern is an input pattern for which the modified design produces a different output than an original design;
using a computer hardware arrangement, providing at least one restoration unit into the design, wherein the at least one restoration unit is configured to (i) produce at least one error-free output when a correct secret key is applied to the at least one restoration unit and (ii) produce at least one erroneous output when an incorrect key is applied to the at least one restoration unit; and
performing at least one of:
(i) determining that the design and the at least one restoration unit produce at least one erroneous output with respect an original design for only a pre-determined constant number of incorrect keys based on at least one input pattern, or
(ii) modifying the at least one logic gate based on a security-aware synthesis procedure which is configured to reduce at least one design metric while ensuring that k−log 2 c is greater than a target security level, and wherein k is a key size and c is a number of cube.

18. A system for modifying a design of at least one integrated circuit (IC), comprising:
a data storage device configured to store a set of computer-executable instructions thereon or therein; and
a processor configured to perform the set of computer-executable instructions;
wherein the set of computer-executable instruction include:
modifying at least one logic gate in the design for at least one protected input pattern, wherein the at least one protected input pattern is an input pattern for which the modified design produces a different output than an original design;
providing at least one restoration unit into the design, wherein the at least one restoration unit is configured to (i) produce at least one error-free output when a correct secret key is applied to the at least one restoration unit and (ii) produce at least one erroneous output when an incorrect key is applied to the at least one restoration unit; and
performing at least one of:
(i) determining that the design and the at least one restoration unit produce at least one erroneous output with respect an original design for only a pre-determined constant number of incorrect keys based on at least one input pattern, or
(ii) modifying the at least one logic gate based on a security-aware synthesis procedure which is configured to reduce at least one design metric while ensuring that k−log 2 c is greater than a target security level, and wherein k is a key size and c is a number of cube.

19. The method of claim 17 , wherein the at least one design metric includes at least one of (i) a power, (ii) an area, or (iii) a delay.

20. The system of claim 18 , wherein the at least one design metric includes at least one of (i) a power, (ii) an area, or (iii) a delay.

Assignees

• Univ New York
• Univ Texas

Inventors

• Sinanoglu Ozgur
• Rajendran Jeyavijayan
• Yasin Muhammad

Classifications

• G06F21/73 Primary

  by creating or determining hardware identification, e.g. serial numbers · CPC title

• G06F21/00

  Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity · CPC title

• G06F16/252

  between a Database Management System and a front-end application · CPC title

• G06F16/2343 Primary

  Locking methods, e.g. distributed locking or locking implementation details · CPC title