Device, system and method to facilitate disaster recovery for a multi-processor platform

Patent metadata

Field	Value
Publication number	US-10990534-B2
Application number	US-201916264447-A
Country	US
Kind code	B2
Filing date	Jan 31, 2019
Priority date	Jan 31, 2019
Publication date	Apr 27, 2021
Grant date	Apr 27, 2021

Abstract

Techniques and mechanisms for capturing an image of processor state at one node of multiple nodes of a multi-processor platform, where the processor state includes some version of data which the node retrieved from another node of the platform. In an embodiment, a disruption of power is detected when a processor of a first node has a cached version of data which was retrieved from a second node. In response to detection of the disruption, the data is saved to a system memory of the first node as part of an image of the processor's state. The image further comprises address information, corresponding to the data, which indicates a memory location at the second node. In another embodiment, processor state is restored during a boot-up of the node, wherein the state includes the captured version of data which was previously retrieved from the second node.

First claim

What is claimed is:

1. A circuit device comprising:
a first processor to couple to a first memory, wherein a first node is to comprise the first processor and the first memory, wherein the first processor comprises:
a first cache to cache first data based on an execution of a software process by the first processor, the execution while the first node is coupled to a second node which comprises a second processor and a second memory, wherein, on behalf of the software process, the first node is to access second data at a memory location of the second memory, wherein the first data is to comprise a cached version of the second data, and wherein the first data corresponds to first address information which indicates the memory location of the second memory;
first circuitry coupled to detect a power disruption event while the first data is cached at the first cache;
second circuitry coupled to the first circuitry, wherein, based on the power disruption event, the second circuitry is to:
interrupt a software execution pipeline of the first processor;
terminate communications between the first node and the second node; and
capture an image of a state of the first processor, comprising the second circuitry to flush the first cache to a reserved region of the first memory, wherein the second circuitry is to write both the first data and the first address information to the reserved region; and

third circuitry to generate a signal after the image is captured, the signal to enable a shutdown of the first processor based on the power disruption event.

2. The circuit device of claim 1 , wherein the first circuitry is to detect the power disruption event while third data is cached at the first processor, wherein the third data corresponds to second address information which represents a memory location of the first memory, wherein the second circuitry to flush the first cache further comprises the second circuitry to write both the third data and the second address information to the reserved region.

3. The circuit device of claim 1 , further comprising the second node, wherein the first circuitry is to detect the power disruption event while third data is cached at the second processor, wherein the third data corresponds to second address information which indicates a second memory location of the first memory, wherein the second processor comprises:
fourth circuitry which, responsive to an indication of the power disruption event, is to:
interrupt a pipeline of the second processor;
capture an image of a state of the second processor, comprising the fourth circuitry to flush a second cache of the second processor to a second reserved region of the second memory, wherein the fourth circuitry to flush the second cache comprises the fourth circuitry to write both the third data and the second address information to the second reserved region.

4. The circuit device of claim 1 , wherein the second circuitry is to capture the image according to an allocation of multiple caches of the first processor each to a different respective sub-region of the reserved region.

5. The circuit device of claim 1 , wherein the second circuitry to terminate the communications comprises the second circuitry to receive an acknowledgement that a link between the first node and the second node is blocked, wherein, responsive to the first circuitry, the second circuitry is further to flush the software execution pipeline of the first processor before the second circuitry is to capture the image.

6. The circuit device of claim 1 , wherein the second circuitry to flush the first cache of the first processor to the reserved region comprises the second circuitry to preserve a relative order of data cached by respective lines of the cache.

7. The circuit device of claim 1 , wherein any cached data which is to be flushed from the first processor to the second node is to be flushed independent of the power disruption event.

8. The circuit device of claim 1 , wherein the first processor further comprises:
fourth circuitry to detect a boot-up of the first processor;
fifth circuitry, responsive to the fourth circuitry, to:
perform an access of the image at the reserved region; and
based on the access, to write the first data and the first address information to the first cache of the first processor.

9. The circuit device of claim 1 , wherein the second circuitry to capture the image comprises the second circuitry to write the image to a volatile memory.

10. The circuit device of claim 9 , wherein the second circuitry to capture the image further comprises the second circuitry to write the image to a non-volatile memory after the image is written to the volatile memory.

11. The circuit device of claim 1 , further comprising:
fourth circuitry, coupled between a core of the first processor and the first memory, to perform a hash calculation, wherein the second circuitry is further to disable the fourth circuitry in response to the first circuitry, wherein the second circuitry is to capture the image while the fourth circuitry is disabled.

12. A system comprising:
a first node comprising:
a first memory; and
a first processor couple to the first memory, wherein the first processor comprises:
a first cache to cache first data based on an execution of a software process by the first processor, the execution while the first node is coupled to a second node which comprises a second processor and a second memory, wherein, on behalf of the software process, the first node is to access second data at a memory location of the second memory, wherein the first data is to comprise a cached version of the second data, and wherein the first data corresponds to first address information which indicates the memory location of the second memory;
first circuitry coupled to detect a power disruption event while the first data is cached at the first cache;
second circuitry coupled to the first circuitry, wherein, based on the power disruption event, the second circuitry is to:
interrupt a software execution pipeline of the first processor;
terminate communications between the first node and the second node; and
capture an image of a state of the first processor, comprising the second circuitry to flush the first cache to a reserved region of the first memory, wherein the second circuitry is to write both the first data and the first address information to the reserved region; and

third circuitry to generate a signal after the image is captured, the signal to enable a shutdown of the first processor based on the power disruption event; and

a display device coupled to the first node, the display device to display an image based on the first data.

13. The system of claim 12 , wherein the second circuitry is to capture the image according to an allocation of multiple caches of the first processor each to a different respective sub-region of the reserved region.

14. The system of claim 12 , wherein the second circuitry to flush the first cache of the first processor to the reserved region comprises the second circuitry to preserve a relative order of data cached by respective lines of the first cache.

15. The system of claim 12 , wherein the first processor further comprises:
fourth circuitry to detect a boot-up of the first processor;
fifth circuitry, responsive to the fourth circuitry, to:
perform an access of the image at the reserved region; and
based on the access, to write the first data and the first address information to the first cache of the first processor.

16. The system of claim 12 , wherein the first node further

Assignees

• Intel Corp

Inventors

• Chen Wei
• Nallusamy Eswaramoorthi
• Novakovsky Larisa
• Schmisseur Mark
• Rasmussen Eric
• Van Doren Stephen
• Liu Yen-Cheng

Classifications

• G06F1/30 Primary

  Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations (for resetting only G06F1/24) · CPC title

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title

• G06F12/0891 Primary

  using clearing, invalidating or resetting means · CPC title

• G06F12/0897

  with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811) · CPC title

• G06F12/0802

  Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches · CPC title