Performance optimizations for emulators

US10990423B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10990423-B2
Application numberUS-201916403158-A
CountryUS
Kind codeB2
Filing dateMay 3, 2019
Priority dateOct 1, 2015
Publication dateApr 27, 2021
Grant dateApr 27, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

One embodiment illustrated herein includes a method that may be practiced in a computing environment with a guest architecture running a native architecture system. The method includes acts for handling function calls. The method includes receiving a call to a hybrid binary, wherein the call is in a format for the guest architecture. The hybrid binary includes a native function compiled into a native architecture binary code using guest architecture source code, an interoperability thunk to handle an incompatibility between the guest architecture and the native architecture, and native host remapping metadata that is usable by an emulator to redirect native host callable targets to the interoperability thunk. The method further includes invoking the interoperability thunk to allow the native function in the hybrid binary to be executed natively on the native architecture system.

First claim

Opening claim text (preview).

What is claimed is: 1. A method, implemented at a computer system that includes at least one processor, for handling native and guest function calls within an environment with a guest architecture running within a native architecture system, the method comprising: receiving a call to a hybrid binary, wherein the call uses a function calling format having an incompatibility with the native architecture system, and wherein the hybrid binary comprises: a native function compiled into native binary code that is natively executable on the native architecture, the native binary code being generated from source code based on using one or more preprocessor defines associated with targeting the guest architecture; an interoperability thunk comprising code that is executable by the native architecture and that is configured to handle at least one incompatibility between how the guest architecture and the native architecture pass data between functions, the interoperability thunk comprising at least one of (i) an interoperability pop thunk comprising code that is executable by the native architecture and that is configured to pop data off a stack and into a register, or (ii) an interoperability push thunk comprising code that is executable by the native architecture and that is configured to push data onto the stack; and native host remapping metadata that is usable by an emulator to redirect native host callable targets to the interoperability thunk; and as a result of receiving the call, invoking the interoperability thunk to handle the incompatibility with the native architecture system, enabling the call to invoke the native function within the hybrid binary in order to natively execute the native binary code on the native architecture system. 2. The method of claim 1 , wherein the interoperability thunk comprises the interoperability pop thunk. 3. The method of claim 1 , wherein the interoperability thunk comprises the interoperability push thunk. 4. The method of claim 1 , wherein the native host remapping metadata comprises an array of remap entries. 5. The method of claim 1 , wherein the hybrid binary also comprises configuration data that identifies function targets that are written in native code. 6. The method of claim 5 , wherein the configuration data comprises a bitmap. 7. The method of claim 6 , wherein state of a bit in the bitmap indicates either, that a target corresponding to the bit is native code; or that the target is guest code or is an invalid target. 8. A computer system comprising: at least one processor; and at least one computer-readable media having stored thereon computer-executable instructions that are executable by the at least one processor to cause the computer system to handle native and guest function calls within an environment with a guest architecture running within a native architecture system, the computer-executable instructions including instructions that are executable by the at least one processor to perform at least: receive a call to a hybrid binary, wherein the call uses a function calling format having an incompatibility with the native architecture system, and wherein the hybrid binary comprises: a native function compiled into native binary code that is natively executable on the native architecture, the native binary code being generated from source code based on using one or more preprocessor defines associated with targeting the guest architecture; an interoperability thunk comprising code that is executable by the native architecture and that is configured to handle at least one incompatibility between how the guest architecture and the native architecture pass data between functions, the interoperability thunk comprising at least one of (i) an interoperability pop thunk comprising code that is executable by the native architecture and that is configured to pop data off a stack and into a register, or (ii) an interoperability push thunk comprising code that is executable by the native architecture and that is configured to push data onto the stack; and native host remapping metadata that is usable by an emulator to redirect native host callable targets to the interoperability thunk; and as a result of receiving the call, invoke the interoperability thunk to handle the incompatibility with the native architecture system, enabling the call to invoke the native function within the hybrid binary in order to natively execute the native binary code on the native architecture system. 9. The computer system of claim 8 , wherein the interoperability thunk comprises the interoperability pop thunk. 10. The computer system of claim 8 , wherein the interoperability thunk comprises the interoperability push thunk. 11. The computer system of claim 8 , wherein the native host remapping metadata comprises an array of remap entries. 12. The computer system of claim 8 , wherein the hybrid binary also comprises configuration data that identifies function targets that are written in native code. 13. The computer system of claim 12 , wherein the configuration data comprises a bitmap. 14. The computer system of claim 13 , wherein state of a bit in the bitmap indicates either, that a target corresponding to the bit is native code; or that the target is guest code or is an invalid target. 15. A computer program product comprising at least one hardware storage device having stored thereon computer-executable instructions that are executable by at least one processor to cause a computer system to handle native and guest function calls within an environment with a guest architecture running within a native architecture system, the computer-executable instructions including instructions that are executable by the at least one processor to perform at least: receive a call to a hybrid binary, wherein the call uses a function calling format having an incompatibility with the native architecture system, and wherein the hybrid binary comprises: a native function compiled into native binary code that is natively executable on the native architecture, the native binary code being generated from source code based on using one or more preprocessor defines associated with targeting the guest architecture; an interoperability thunk comprising code that is executable by the native architecture and that is configured to handle at least one incompatibility between how the guest architecture and the native architecture pass data between functions, the interoperability thunk comprising at least one of (i) an interoperability pop thunk comprising code that is executable by the native architecture and that is configured to pop data off a stack and into a register, or (ii) an interoperability push thunk comprising code that is executable by the native architecture and that is configured to push data onto the stack; and native host remapping metadata that is usable by an emulator to redirect native host callable targets to the interoperability thunk; and as a result of receiving the call, invoke the interoperability thunk to handle the incompatibility with the native architecture system, enabling the call to invoke the native function within the hybrid binary in order to natively execute the native binary code on the native architecture system. 16. The computer system of claim 15 , wherein the interoperability thunk comprises the interoperability pop thunk. 17. The computer system of claim 15 , wherein the interoperability thunk comprises the interoperability push thunk. 18. The computer system of claim 15 , wherein the native host remappin

Assignees

Inventors

Classifications

  • Runtime code conversion or optimisation · CPC title

  • Executing subprograms · CPC title

  • Involving translation to a different instruction set architecture, e.g. just-in-time translation in a JVM · CPC title

  • G06F9/455Primary

    Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines · CPC title

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What does patent US10990423B2 cover?
One embodiment illustrated herein includes a method that may be practiced in a computing environment with a guest architecture running a native architecture system. The method includes acts for handling function calls. The method includes receiving a call to a hybrid binary, wherein the call is in a format for the guest architecture. The hybrid binary includes a native function compiled into a …
Who is the assignee on this patent?
Microsoft Technology Licensing Llc
What technology area does this patent fall under?
Primary CPC classification G06F9/45516. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Apr 27 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).