Memory module capable of reducing power consumption and semiconductor system including the same

Patent metadata

Field	Value
Publication number	US-10990301-B2
Application number	US-201815884693-A
Country	US
Kind code	B2
Filing date	Jan 31, 2018
Priority date	Feb 28, 2017
Publication date	Apr 27, 2021
Grant date	Apr 27, 2021

Abstract

A memory module may include a memory device and a power controller. The memory device may operate by being supplied with a first memory power supply voltage and a second memory power supply voltage. The power controller may receive a first power supply voltage and a second power supply voltage from a power source, and supply the first memory power supply voltage and the second memory power supply voltage by changing levels of the first power supply voltage and the second power supply voltage based on operation state information.

First claim

What is claimed is:

1. A memory module comprising:
a memory device configured to operate by being supplied with a first memory power supply voltage and a second memory power supply voltage; and
a power controller circuit configured to receive a first power supply voltage and a second power supply voltage from a power source, and supply the first memory power supply voltage and the second memory power supply voltage by changing levels of the first power supply voltage and the second power supply voltage based on operation state information,
wherein the power controller circuit changes the level of the first power supply voltage to supply the first memory power supply voltage according to a temperature of the memory device, and supplies the second memory power supply voltage having the same level as the second power supply voltage regardless of the temperature of the memory device.

2. The memory module according to claim 1 , wherein the operation state information includes operation mode information and temperature information about the memory device.

3. The memory module according to claim 2 , wherein the operation mode information of the memory device includes information on a normal operation, a first standby operation and a second standby operation.

4. The memory module according to claim 1 , wherein, when the temperature of the memory device is a first temperature, the power controller circuit supplies the first memory power supply voltage having substantially the same level as the first power supply voltage and supplies the second memory power supply voltage having substantially the same level as the second power supply voltage.

5. The memory module according to claim 4 , wherein, when the temperature of the memory device is a second temperature lower than the first temperature, the power controller circuit supplies the first memory power supply voltage having a lower level than the first power supply voltage and supplies the second memory power supply voltage having substantially the same level as the second power supply voltage.

6. The memory module according to claim 4 , wherein, when the temperature of the memory device is a third temperature higher than the first temperature, the power controller circuit supplies the first memory power supply voltage having a higher level than the first power supply voltage and supplies the second memory power supply voltage having substantially the same level as the second power supply voltage.

7. The memory module according to claim 1 , wherein the power controller circuit comprises:
a power supply voltage control circuit configured to generate the operation state information based on a temperature flag, and generate a first voltage control signal and a second voltage control signal according to the operation state information;
a first power supply voltage generation circuit configured to generate the first memory power supply voltage by changing the level of the first power supply voltage based on the first voltage control signal; and
a second power supply voltage generation circuit configured to generate the second memory power supply voltage by changing the level of the second power supply voltage based on the second voltage control signal.

8. The memory module according to claim 7 , wherein the power supply voltage control circuit comprises:
an operation state determining circuit configured to generate the operation state information based on the temperature flag;
a first voltage control signal generator configured to generate the first voltage control signal based on the operation state information; and
a second voltage control signal generator configured to generate the second voltage control signal based on the operation state information.

9. The memory module according to claim 1 , wherein the first power supply voltage has a higher level than the second power supply voltage.

10. A memory module comprising:
a memory device configured to operate by being supplied with a first memory power supply voltage and a second memory power supply voltage; and
a power controller circuit configured to receive a first power supply voltage and a second power supply voltage from a power source,
to supply the first memory power supply voltage having substantially the same level as the first power supply voltage, in a normal operation and a first standby operation of the memory device,
to block the first power supply voltage from being supplied as the first memory power supply voltage, in a second standby operation,
to supply the second memory power supply voltage having substantially the same level as the second power supply voltage, in the normal operation of the memory device, and
to supply the second memory power supply voltage having a lower level than the second power supply voltage, in the first standby operation and the second standby operation,
wherein the first power supply voltage has a higher level than the second power supply voltage.

11. The memory module according to claim 10 , wherein the power controller circuit supplies a low voltage as the first memory power supply voltage in the second standby operation, and the low voltage has a lower level than the first power supply voltage.

Assignees

• Sk Hynix Inc

Inventors

• Kim Jung Hyun

Classifications

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F1/3275 Primary

  Power saving in memory, e.g. RAM, cache · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G11C11/40626

  Temperature related aspects of refresh operations · CPC title

• G06F3/0625 Primary

  Power saving in storage systems · CPC title