Software assist memory module hardware architecture

Patent metadata

Field	Value
Publication number	US-10990291-B2
Application number	US-201715620086-A
Country	US
Kind code	B2
Filing date	Jun 12, 2017
Priority date	Jun 12, 2017
Publication date	Apr 27, 2021
Grant date	Apr 27, 2021

Abstract

A software assist module of a system memory coupled to a host processor provides the ability to offload software operations from the host processor. The software assist module includes a first memory accessed by the host processor via a first chip select signal. The software assist module also includes a software assist controller accessed by the host processor via a second chip select signal. The software assist controller is configured to intercept data related to a software function offloaded from the host processor, where the data is intercepted from a first chip select signal used to access the first memory. The software assist controller utilizes the intercepted data to perform the offloaded function. Based on configuration instructions provided by the host processor via the second chip select signal, the software assist module performs the offloaded function incrementally as function data is intercepted or as a single operation after all data for a function has been intercepted.

First claim

The invention claimed is:

1. A DIMM (Dual In-line Memory Module) comprised of a plurality of memory chips, wherein the DIMM is coupled to a host processor of an IHS (Information Handling System) via a DIMM socket of a motherboard of the IHS, the DIMM comprising:
a first memory chip of the DIMM coupled to the motherboard DIMM socket of the IHS, wherein the first memory chip is accessed by the host processor of the IHS via a first chip select signal as a first rank of the DIMM, wherein memory locations of the first rank are accessible simultaneously by the host processor; and
a software assist controller mounted on a first side of the DIMM coupled to the motherboard DIMM socket of the IHS, wherein the software assist controller is accessed by the host processor via a second chip select signal as a second rank of the DIMM, wherein the software assist controller is configured to:
intercept data related to a storage operation offloaded from the host processor of the IHS, wherein the data is intercepted from the first chip select signal used to access the first memory chip of the DIMM, and wherein the storage operation comprises an operation on a data storage system accessed by the host controller via a first bus interface;
receive configuration instructions for the offloaded storage operation from the host processor via the second chip select signal of the DIMM; and
perform the offloaded storage operation utilizing the intercepted data.

2. The memory module of claim 1 , wherein the data storage system comprises a RAID (Redundant Array of Independent Disks) storage system.

3. The memory module of claim 2 , wherein the offloaded storage operation comprises a RAID parity operation.

4. The memory module of claim 1 , wherein, based on the received configuration instructions, the software assist controller is further configured to:
perform the offloaded storage operation incrementally as a plurality of data portions for performing the offloaded storage operation are intercepted on the first chip select signal.

5. The memory module of claim 1 , wherein, based on the received configuration instructions, the software assist controller is further configured to:
delay the performing of the offloaded storage operation until all of the data related to the offloaded storage operation is intercepted on the first chip select signal.

6. The memory module of claim 1 , wherein the software assist controller comprises a plurality of registers storing parameters of the configuration instructions received via the second chip select signal.

7. The memory module of claim 6 , wherein the configuration instructions stored to the plurality of registers comprise memory addresses of the data storage system, wherein the memory addresses correspond to data associated with the offloaded storage operation.

8. The IHS claim 6 , wherein the software assist controller comprises a plurality of registers storing parameters of the configuration instructions received via the second chip select signal.

9. A memory system comprising:
a processor coupled to a memory controller;
a system memory coupled to the memory controller via a memory bus, wherein the system memory comprises a removeable DIMM (Dual In-line Memory Module) coupled to a DIMM socket of a motherboard of an IHS (Information Handling System), and wherein the removeable DIMM comprises a software assist controller mounted on a first side of the removeable DIMM; and
the removeable DIMM comprised of a plurality of memory chips and coupled to the memory controller via a DIMM motherboard socket of the IHS, wherein the removeable DIMM comprises a first memory chip accessed by the memory controller via a first chip select signal as a first rank of the DIMM, wherein memory locations of the first rank are accessible simultaneously by the processor, and further comprising the software assist controller mounted on a first side of the DIMM and accessed by the memory controller via a second chip select signal as a second rank of the DIMM, wherein the software assist controller mounted on the DIMM is configured to:
intercept data related to a storage operation offloaded from the processor, wherein the data is intercepted from the first chip-select signal used to access the first memory chip of the DIMM, and wherein the storage operation comprises an operation on a data storage system accessed by the processor via a first bus interface;
receive configuration instructions for the offloaded storage operation from the processor via the second chip select signal of the DIMM; and
perform the offloaded storage operation utilizing the intercepted data.

10. The memory system of claim 9 , wherein the data storage system comprises a RAID (Redundant Array of Independent Disks) storage system.

11. The memory system of claim 10 , wherein the offloaded storage operation comprises a RAID parity operation.

12. The memory system of claim 9 , wherein, based on the received configuration instructions, the software assist controller is further configured to:
perform the offloaded storage operation incrementally as a plurality of data portions for performing the offloaded storage operation are intercepted on the first chip select signal.

13. The memory system of claim 9 , wherein, based on the received configuration instructions, the software assist controller is further configured to:
delay the performing of the offloaded storage operation until all of the data related to the offloaded storage operation is intercepted on the first chip select signal.

14. The memory system of claim 9 , wherein the software assist controller comprises a plurality of registers storing parameters of the configuration instructions received via the second chip select signal.

15. The memory system of claim 14 , wherein the configuration instructions stored to the plurality of registers comprise memory addresses of the data storage system, wherein the memory addresses correspond to data associated with the offloaded storage operation.

16. An IHS (Information Handling System) comprising:
a processor coupled to a memory controller;
a system memory coupled to the memory controller via a memory bus, wherein the system memory comprises a removable memory module coupled to a memory socket of a motherboard of an IHS (Information Handling System), and wherein the removeable memory module comprises a software assist controller mounted on a first side of the removeable memory module, and wherein the removeable memory module comprises at least one of a DIMM (Dual In-line Memory Module), a Dual In-line Package (DIP) memory module, a Single In-line Pin Package (SIPP) memory module, a Single In-line Memory Module (SIMM), and/or a Ball Grid Array (BGA) memory module; and
the removable memory module comprised of a plurality of memory chips and coupled to the memory controller via a motherboard socket of the IHS, wherein the removeable memory module comprises a first memory chip accessed by the memory controller via a first chip select signal as a first rank of the memory module, wherein memory locations of the first rank are accessible simultaneously by the host processor, and further comprising the software assist controller mounted on a first side of the memory module and accessed by the memory controller via a second chip select signal as a second rank of the memory module, wherein the software assist controller is configured to:
intercept data related to a storage operation offloaded from the processor, wherein the data is intercepted from the first chip-select signal used to access the first memory chip, and wherein the storage operation

Assignees

• Dell Products Lp

Inventors

• Berke Stuart
• Kotzur Gary

Classifications

• G06F2212/282

  Partitioned cache · CPC title

• G06F2212/461

  Sector or disk block · CPC title

• G06F12/0848

  Partitioned cache, e.g. separate instruction and operand caches · CPC title

• G06F2212/311

  In host system · CPC title

• G06F12/0873

  Mapping of cache memory to specific storage devices or parts thereof · CPC title