Method and system for providing a sleep mode to a configurable logic block using an intermittent power saving logic

Patent metadata

Field	Value
Publication number	US-10990160-B2
Application number	US-201916361112-A
Country	US
Kind code	B2
Filing date	Mar 21, 2019
Priority date	Mar 21, 2019
Publication date	Apr 27, 2021
Grant date	Apr 27, 2021

Abstract

A programmable semiconductor integrated circuit fabricated on a single microchip device capable of being selectively programmed to perform one or more logic functions provides a sleep mode using an intermittent power saving logic. The circuit includes configurable logic blocks (“LB”), memory, switch, and sleep controller. While LB can enter a power saving sleep mode (“PSSM”) in accordance with its power supply, the memory stores the configuration information for the LB. The switch is configured to manage the LB power supply based on a configurable sleep signal for facilitating the PSSM. The sleep controller facilitates generation of the configurable sleep signal in response to the signal from a power saving output port associated with the LB.

First claim

What is claimed is:

1. A semiconductor device to perform one or more logic functions with a power saving logic, comprising:
a first circuit, containing a plurality of configurable logic blocks (“LBs”) to be selectively programmed to perform one or more logic functions, configured to enter a power saving sleep mode (“PSSM”) in accordance with a first power supply;
a second circuit coupled to the first circuit and configured to have a memory configured to store first configuration information for programming the first circuit;
a switch coupled to the first circuit and configured to switch on the first power supply based on a configurable sleep signal for facilitating a sleep duration of the first circuit; and
a sleeping controller coupled to the switch and configured to gradually elevate voltage of the configurable sleep signal via a programmable charge pumping component in response to a first output signal of the first circuit through a power output port.

2. The device of claim 1 , further comprising an input and output (“I/O”) block coupled to the first circuit and configured to have a plurality of I/O ports including the power saving output port.

3. The device of claim 2 , wherein the I/O block is coupled to a second power supply for supplying a voltage to the plurality of I/O ports to create a high impedance to one or more I/O ports for preventing current flow through the plurality of I/O ports during the PSSM in the first circuit.

4. The device of claim 1 , further comprising a timer coupled to the I/O block and configured to initiate a process of PSSM.

5. The device of claim 1 , wherein the first circuit is a programmable logic block to be programmed to perform various logic functions.

6. The device of claim 1 , wherein the second circuit includes a processor configured to program the first circuit based on information stored in the memory.

7. The device of claim 1 , wherein the switch is a transistor for controlling power supply to the first circuit in response to the first output signal and an output of sleeping controller.

8. The device of claim 1 , wherein the sleeping controller includes a programmable capacitor which can be programmed to determine a sleep duration for the first circuit.

9. A programmable semiconductor integrated circuit fabricated on a single microchip configured to perform the PSSM comprising the device of claim 1 .

10. A method of semiconductor chip to periodically turn off a portion of a programmable logic device for power conservation, the method comprising:
receiving a first output signal with a first voltage from a power saving output port at an input and output (“I/O”) block;
monitoring gradually rising of voltage level of the first output voltage to a high impedance (“Hi-Z”) indicating that at least a portion of a programmable logic block (“PLB”) is in a power saving sleep mode (“PSSM”);
activating a programmable voltage pump to gradually store charges in a capacitor in accordance with the first voltage; and
turning on a switch in response to the first output signal and the stored charges in the capacitor to wake up at least a portion of sleeping PLB by supplying power to the sleeping PLB.

11. The method of claim 10 , further comprising driving a zero-voltage representing logic zero on the first output signal at the power saving output port for facilitating placing at least a portion of the PLB into the PSSM.

12. The method of claim 10 , further comprising pulling a plurality of I/O ports in the I/O block to the Hi-Z when the PLB is in the PSSM.

13. The method of claim 10 , further comprising generating a logic zero voltage periodically by a timer at the power saving output port for facilitating the PSSM.

14. The method of claim 10 , wherein receiving a first output signal includes providing a relatively low voltage signal to the power saving output port when a sleep cycle is initiated by the timer.

15. The method of claim 10 , wherein monitoring gradually rising of voltage level of the first output voltage to a high impedance (“Hi-Z”) includes preventing communication between the PLB and external devices when voltage reaches Hi-Z.

16. The method of claim 10 , wherein activating a programmable voltage pump includes charging a programmable capacitor which facilitates duration of sleeping cycle.

17. The method of claim 10 , wherein turning on a switch includes drawing power from a Vcc power supply to the PLB to wake up the sleeping PLB based on configuration data stored in a nonvolatile memory.

18. A method of semiconductor chip periodically turning off a portion of a programmable logic device for power conservation, the method comprising:
switching a programmable logic block (“PLB”) into a power saving sleep mode (“PSSM”) when a switch of power control is turned off;
driving a plurality of input and output (“I/O”) ports of an I/O block to high impedance (“Hi-Z”) to minimize current flows through the plurality of I/O ports;
receiving a first output signal with a first voltage from a power saving output port of the plurality of I/O ports;
monitoring gradually rising of voltage level of the first output voltage to Hi-Z; and
activating a programmable voltage pump to gradually store charges in a capacitor in accordance with the first voltage.

19. The method of claim 18 , further comprising turning on the switch in response to the first output signal and the stored charges in the capacitor to wake up the PLB.

20. The method of claim 18 , further comprising generating a logic zero voltage periodically by a timer for facilitating activation of the PSSM.

21. An apparatus containing programmable logic blocks having a power saving logic, comprising:
a device containing a programmable counter clocked by a clock and configured to provide a start-sleep signal which facilitates generation of a power saving sleep mode (“PSSM”) control signal;
a programmable device coupled to the device via a connection and configured to have field programmable gate arrays (“FPGA”), wherein the FPGA includes,
configurable logic blocks (“LBs”) configured to be selectively programmed to perform one or more logic functions and configured to enter a power saving sleep mode (“PSSM”);
a control logic coupled to the configurable LBs and having a memory for storing configuration information for programming the configurable LBs;
a switch coupled to the configurable LBs and configured to manage power supply to the configurable LBs based on the PSSM control signal received from the device; and
a switchable intermittent power saving (“IPS”) logic coupled to the switch to provide the PSSM control signal for placing at least a portion of the configurable LBs into the PSSM during an operation.

22. The apparatus of claim 21 , wherein the device is a secondary semiconductor microchip and facilitates processing power saving instructions.

23. The apparatus of claim 22 , wherein the power saving instructions determine when the FPGA wakes.

24. The apparatus of claim 22 , wherein the power saving instructions determine when the FPGA sleeps.

25. The apparatus of claim 21 , wherein the FPGA is a programmable logic block configured to be programmed to perform various logic functions.

Assignees

• Zhu Jinghui
• Gowin Semiconductor Corp

Inventors

• Zhu Jinghui

Classifications

• G06F1/3278

  Power saving in modem or I/O interface · CPC title

• G06F30/34 Primary

  for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title

• G06F1/3246

  by software initiated power-off · CPC title

• G06F1/3296 Primary

  by lowering the supply or operating voltage · CPC title

• G06F9/4418

  Suspend and resume; Hibernate and awake · CPC title