Guaranteed data compression using intermediate compressed data

Patent metadata

Field	Value
Publication number	US-10985776-B2
Application number	US-202016882854-A
Country	US
Kind code	B2
Filing date	May 26, 2020
Priority date	Jun 29, 2018
Publication date	Apr 20, 2021
Grant date	Apr 20, 2021

Abstract

Methods for converting an n-bit number into an m-bit number for situations where n>m and also for situations where n<m, where n and m are integers. The methods use truncation or bit replication followed by the calculation of an adjustment value which is applied to the replicated number.

First claim

What is claimed is:

1. A method of mapping an input n-bit number to an output m-bit number, where n and m are integers and n>m, the method comprising:
determining, in a truncation hardware unit, an intermediate m-bit number;
setting, in a look-up logic hardware unit, an adjustment value based on the input n-bit number; and
adding, in an increment/decrement hardware unit, the adjustment value to the intermediate m-bit number to generate the output m-bit number.

2. The method according to claim 1 , wherein the look-up logic hardware unit comprises an arrangement of AND and OR logic blocks and wherein setting an adjustment value based on the input n-bit number comprises:
for each of a plurality of pre-determined subsets of the bits of the input n-bit number, using a plurality of AND logic blocks to compare the subset to a pre-defined bit sequence; and
in response to identifying a match between a subset and its corresponding pre-defined bit sequence, setting the adjustment value to a value associated with the pre-defined bit sequence.

3. Hardware logic configured to perform the method of claim 1 , optionally wherein the hardware logic is embodied in hardware on an integrated circuit.

4. A data compression unit comprising the hardware logic according to claim 3 .

5. A non-transitory computer readable storage medium having stored thereon computer executable code that when executed causes at least one processor to perform the method as set forth in claim 1 .

6. A method of mapping an input n-bit number to an output m-bit number, where n and m are integers and n<m, the method comprising:
determining, in a replication hardware unit, an intermediate m-bit number;
setting, in a look-up logic hardware unit: an adjustment value based on the input n-bit number; and
adding, in an increment/decrement hardware unit, the adjustment value to the intermediate m-bit number to generate the output m-bit number.

7. The method according to claim 6 , wherein if m>2n, determining an intermediate m-bit number comprises:
appending (k−1) repetitions of the input n-bit number to the input n-bit number followed by r most significant bits of the input n-bit number, where k=└(m/n)┘ and r=m mod n.

8. The method according to claim 6 , wherein the look-up logic hardware unit comprises an arrangement of AND and OR logic blocks and wherein setting an adjustment value based on the input n-bit number comprises:
for each of a plurality of pre-determined subsets of the bits of the input n-bit number, using a plurality of AND logic blocks to compare the subset to a pre-defined bit sequence; and
in response to identifying a match between a subset and its corresponding pre-defined bit sequence, setting the adjustment value to a value associated with the pre-defined bit sequence.

9. Hardware logic configured to perform the method of claim 6 , optionally wherein the hardware logic is embodied in hardware on an integrated circuit.

10. A data compression unit comprising the hardware logic according to claim 9 .

11. A non-transitory computer readable storage medium having stored thereon computer executable code that when executed causes at least one processor to perform the method as set forth in claim 6 .

12. Hardware logic arranged to map an input n-bit number to an output m-bit number, where n and m are integers and n>m, the hardware logic comprising:
a truncation hardware unit arranged to determine an intermediate m-bit number;
a look-up logic hardware unit arranged to set an adjustment value based on the input n-bit number; and
an increment/decrement hardware unit arranged to add the adjustment value to the intermediate m-bit number to generate the output m-bit number.

13. A data compression unit comprising the hardware logic according to claim 9 .

14. A method of manufacturing, using an integrated circuit manufacturing system, hardware logic as claimed in claim 12 .

15. A non-transitory computer readable storage medium having stored thereon an integrated circuit dataset description that, when processed in an integrated circuit manufacturing system, configures the integrated circuit manufacturing system to manufacture hardware logic as claimed in claim 12 .

16. An integrated circuit manufacturing system configured to manufacture hardware logic as claimed in claim 12 .

17. An integrated circuit manufacturing system comprising:
a non-transitory computer readable storage medium having stored thereon a computer readable dataset description of an integrated circuit that describes hardware logic as claimed in claim 12 ;
a layout processing system configured to process the integrated circuit description so as to generate a circuit layout description of an integrated circuit embodying the hardware logic; and
an integrated circuit generation system configured to manufacture the hardware logic according to the circuit layout description.

Assignees

• Imagination Tech Ltd

Inventors

• Fenney Simon

Classifications

• G06F1/035

  Reduction of table size {(G06F1/0314 takes precedence)} · CPC title

• H03M7/3071

  Prediction · CPC title

• H04N19/184

  the unit being bits, e.g. of the compressed video stream · CPC title

• H04N19/42 Primary

  characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation (H04N19/635 takes precedence) · CPC title

• G06T1/60

  Memory management · CPC title