Method of calibrating capacitive array of successive approximation register analog-to-digital converter

Patent metadata

Field	Value
Publication number	US-10985771-B2
Application number	US-201916703828-A
Country	US
Kind code	B2
Filing date	Dec 4, 2019
Priority date	Aug 21, 2019
Publication date	Apr 20, 2021
Grant date	Apr 20, 2021

Abstract

A method of calibrating capacitive array of a resistor-capacitor hybrid successive approximation register analog-to-digital converter (RC-hybrid SAR ADC) that includes a high M-bit capacitor DAC and a low N-bit resistor DAC. The method includes: disposing n unit capacitors in each capacitive array of the RC-hybrid SAR ADC, wherein n=2M−1; sorting the capacitors in an ascending order according to their capacitances to form a sorted array, and selecting two capacitors Cu(n/2)*, Cu(n/2+1)* in the middle positions as a least significant bit (LSB) capacitor and a dummy capacitor, respectively; obtaining a new array by forming each capacitor through adding two capacitors which have symmetrical positions with respect to the middle position(s) in the sorted array; and sorting the new array in an ascending order, and selecting the capacitor in the middle position as a higher bit capacitor. The method improves the static and dynamic performance of the SAR ADC.

First claim

What is claimed is:

1. A method for calibrating capacitive array of a resistor-capacitor hybrid successive approximation register analog-to-digital converter (RC-hybrid SAR ADC), wherein the RC-hybrid SAR ADC comprising a high M-bit capacitor DAC and a low N-bit resistor DAC, M represents the bit number of the high M-bit capacitor DAC, and N represents the bit number of the low N-bit capacitor DAC; the method comprising:
1) disposing n unit capacitors in a positive capacitive array and a negative capacitive array of the RC-hybrid SAR ADC, respectively, and labeling the n unit capacitors as: C u1 , C u2 , C u3 , C u4 , . . . , C u(n−1) , C un , wherein n=2 M−1 ;
2) sorting the n unit capacitors in an ascending order according to their capacitances, and recording them as: C u1 *, C u2 *, C u3 *, C u4 *, . . . , C u(n−1) *, C un *;
3) selecting the capacitor C u(n/2) * in a (2 M−1 /2 (0+1) =2 M−(0+2 ) th position of the capacitances as a least significant bit (LSB) capacitor in each of the positive capacitive array and the negative capacitive array of the RC-hybrid SAR ADC, wherein the LSB capacitor has a bit position number of 0; and selecting the capacitor C u(n/2+1) * in (2 M−2 +1) th position of the capacitances as a dummy capacitor in each of the positive capacitive array and the negative capacitive array of the RC-hybrid SAR ADC;
4) combining C u1 * and C un * into A 1 , and combining C u2 * and C u(n−1) * into A 2 , . . . , and combining C u(n/2−1) * and C u(n/2+2) *; into A (n/2−1) , to yield a first array A i ;
5) sorting the first array A 1 in an ascending order to obtain a second array A i * comprising A 1 *, A 2 *, A 3 *, A 4 *, . . . , A (n/2−1) *; selecting A (n/4) *, which is in a (2 M−1 /2 (1+1) =2 M−(1+2 ) th position of the second array A i *, as a second least significant bit (LSB+1) capacitor in each of the positive capacitive array and the negative capacitive array of the RC-hybrid SAR ADC, wherein the (LSB+1) capacitor has a bit position number of 1;
6) combining A 1 * and A (n/2−1) * into B 1 , combining A 2 * and A (n/2−2) * into B 2 , . . . , A (n/4−1) * and combining A (n/4+1) * into B (n/4−1) , to yield a third array B i ;
7) sorting the third array B i in an ascending order to obtain a fourth array B i * comprising B 1 *, B 2 *, B 3 *, B 4 *, . . . , B (n/4−1) *, and selecting B (n/8) *, which is in a (2 M−1 /2 (2+1) =2 M−(2+2 ) th position of the fourth array A i *, as a third least significant bit (LSB+2) capacitor in each of the positive capacitive array and the negative capacitive array of the RC-hybrid SAR ADC, wherein the (LSB+2) capacitor has a bit position number of 2;
8) repeating 6) and 7) to get other higher bit capacitors in each of the positive capacitive array and the negative capacitive array of the RC-hybrid SAR ADC; and
9) sorting the second to final array E comprising E 1 , E 2 , E 3 in an ascending order to obtain the final array E i * comprising E 1 *, E 2 *, E 3 *, and selecting E 2 *, which is in a (2 M−1 /2 (m−1+1) =2 M−(m−1+2 ) th position of the final array E i *, as a (LSB+m−1) capacitor in each of the positive capacitive array and the negative capacitive array of the RC-hybrid SAR ADC, wherein the (LSB+m−1) capacitor has a bit position number of m−1, m is an integer and larger than 3, and M=m+2;
and combining E 1 * and E 3 * to obtain a (LSB+m) capacitor that is a most significant bit (MSB) capacitor and has a bit position number of m.

Assignees

• Univ Electronic Sci & Tech China

Inventors

• Fan Hua
• Wang Chen
• Lei Peng
• Zhang Dainan
• Feng Quanyuan
• Feng Lang
• Diao Xiaopeng
• Li Dagang
• Zhang Kelin
• Hu Daqian
• Cen Yuanjun

Classifications

• H03M1/68

  with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits · CPC title

• H03M1/0678

  using additional components or elements, e.g. dummy components · CPC title

• H03M1/1009 Primary

  Calibration · CPC title

• H03M1/462

  Details of the control circuitry, e.g. of the successive approximation register · CPC title

• H03M1/1033 Primary

  over the full range of the converter, e.g. for correcting differential non-linearity · CPC title