Methods and apparatus for an amplifier integrated circuit

Patent metadata

Field	Value
Publication number	US-10985718-B2
Application number	US-201916447149-A
Country	US
Kind code	B2
Filing date	Jun 20, 2019
Priority date	Jun 20, 2019
Publication date	Apr 20, 2021
Grant date	Apr 20, 2021

Abstract

Various embodiments of the present technology may provide methods and apparatus for an amplifier integrated circuit. The amplifier integrated circuit may provide two amplifiers, one amplifier set to a low gain bandwidth product to amplify at a higher speed and the other amplifier set to a high gain bandwidth product to amplify at a lower speed. The amplifier integrated circuit may further provide a switching circuit connected to the amplifiers, wherein the switching circuit is responsive to a control signal and operates to selectively activate the high speed amplifier and the low speed amplifier in sequence.

First claim

The invention claimed is:

1. An amplifier integrated circuit (IC), connected to an input terminal and an output terminal, comprising:
a first amplifier having a first gain bandwidth product;
a second amplifier having a second gain bandwidth product that is less than the first gain bandwidth product; and
a control circuit, connected to the first and second amplifiers and responsive to a control signal, comprising a plurality of switches configured to:
selectively connect a first amplifier output to the output terminal of the amplifier IC according to the control signal; and
selectively connect a second amplifier output to the output terminal of the amplifier IC according to the control signal;
wherein:
the plurality of switches comprises a first switch, a second switch, a third switch and a fourth switch;
the first switch is connected to a first output terminal of the first amplifier;
the second switch is connected to a second output terminal of the first amplifier;
the third switch is connected to a first output terminal of the second amplifier; and
the fourth switch is connected to a second output terminal of the second amplifier.

2. The amplifier integrated circuit of claim 1 , wherein:
the first amplifier is connected in parallel with the second amplifier;
an input terminal of the first amplifier and an input terminal of the second amplifier are connected to the input terminal of the amplifier IC; and
an output terminal of the first amplifier and an output terminal of the second amplifier are connected to the output terminal of the amplifier IC.

3. The amplifier integrated circuit of claim 2 , wherein:
the first switch and the second switch are connected in series with an output terminal of the first amplifier and the output terminal of the amplifier IC; and
the third switch and the fourth switch are connected in series with an output terminal of the second amplifier and the output terminal of the amplifier IC.

4. The amplifier integrated circuit of claim 1 , wherein:
the input terminal of the amplifier IC is connected to a first amplifier input; and
the input terminal of the amplifier IC is selectively connected to a second amplifier input.

5. The amplifier integrated circuit of claim 1 , wherein:
the control signal comprises a first value and a second value;
at the first value, the first and second switches are open and the third and fourth switches are closed; and
at the second value, the first and second switches are closed and the third and fourth switches are open.

6. A method of operating an amplifier integrated circuit (IC), comprising:
amplifying a signal with a first amplifier having a first gain bandwidth product and generating a first output signal;
deactivating the first amplifier by selectively disconnecting the first amplifier from an output terminal of the amplifier IC;
activating a second amplifier having a second gain bandwidth product that is less than the first gain bandwidth product by selectively connecting the second amplifier to the output terminal of the amplifier IC;
amplifying the signal with the second amplifier and generating a second output signal; and
charging a capacitor for a first period according to the first output signal and charging the capacitor for a second period according to the second output signal.

7. The method of operating an amplifier integrated circuit of claim 6 , further comprising: generating a control signal, wherein the control signal comprises a first value and a second value.

8. The method of operating an amplifier integrated circuit of claim 6 , wherein deactivating the first amplifier by selectively disconnecting the first amplifier comprises:
opening a first pair of switches according to the control signal, wherein the first pair of switches are connected to an output terminal of the first amplifier.

9. The method of operating an amplifier integrated circuit of claim 6 , wherein activating the second amplifier by selectively connecting the second amplifier further comprises: closing a second set of switches according to the control signal, wherein the second pair of switches are connected to an output terminal of the second amplifier.

10. A system, comprising:
a sensor configured to generate sensor data;
an amplifier integrated circuit (IC) configured to generate an output signal, and comprising:
a main input terminal configured to receive the sensor data; and
a main output terminal;
a first amplifier comprising:
a first input terminal directly connected to the main input terminal; and
a first output terminal selectively connected to the main output terminal; and
wherein the first amplifier has a first gain bandwidth product;

a second amplifier comprising:
a second input terminal connected to the main input terminal; and
a second output terminal connected to the main output terminal; and
wherein a second input terminal has a second gain bandwidth product that is less than the first gain bandwidth product; and

a control circuit, connected to the first and second amplifiers and responsive to a control signal, comprising: a first pair of switches connected between the first output terminal and the main output terminal;

a switched capacitor circuit connected to main output terminal and configured to charge according to the output signal.

11. The system of claim 10 , wherein:
the first amplifier is connected in parallel with the second amplifier; and
the second input terminal is directly connected to the main input terminal.

12. The system of claim 11 , further comprising: a second pair of switches connected between the second output terminal and the main output terminal.

13. The system of claim 10 , wherein the first amplifier is connected in series with the second amplifier.

14. The system of claim 13 , further comprising: a second pair of switches connected between the main input terminal and second input terminal.

15. The system of claim 10 , wherein the control signal comprises a first value and a second value.

16. The system of claim 15 , wherein:
at the first value, the first pair of switches is open and the second pair of switches are closed; and
at the second value, the first pair of switches are closed and the second pair of switches are open.

17. The system of claim 10 , wherein the amplifier IC is configured to charge the switched capacitor for a first period using the first amplifier and charge the switched capacitor for a second period using the second amplifier.

Assignees

• Semiconductor Components Ind Llc

Inventors

• Murata Tsutomu

Classifications

• G01D5/24

  by varying capacitance · CPC title

• H03F2203/45541

  the IC comprising dynamic biasing means, i.e. controlled by the input signal · CPC title

• H03F1/26 Primary

  Modifications of amplifiers to reduce influence of noise generated by amplifying elements · CPC title

• H03F2203/45551

  the IC comprising one or more switched capacitors · CPC title

• H03F3/45636

  by using feedback means (H03F3/45744 takes precedence) · CPC title