Semiconductor device with planar field effect transistor cell

Patent metadata

Field	Value
Publication number	US-10985245-B2
Application number	US-201816220693-A
Country	US
Kind code	B2
Filing date	Dec 14, 2018
Priority date	Dec 15, 2017
Publication date	Apr 20, 2021
Grant date	Apr 20, 2021

Abstract

The disclosure relates to a semiconductor device including a first planar field effect transistor cell and a second planar field effect transistor cell. The first planar field effect transistor cell and the second planar field effect transistor cell are electrically connected in parallel and each include a drain extension region between a channel region and a drain terminal at a first surface of a semiconductor body. A gate electrode of the first field effect transistor cell is electrically connected to a source terminal, and a gate electrode of the second field effect transistor cell is connected to a gate terminal that is electrically isolated from the source terminal.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first planar field effect transistor cell and a second planar field effect transistor cell electrically connected in parallel and each comprising a drain extension region between a channel region and a drain terminal at a first surface of a semiconductor body,
wherein a gate electrode of the first field effect transistor cell is electrically connected to a source terminal,
wherein a gate electrode of the second field effect transistor cell is connected to a gate terminal that is electrically isolated from the source terminal,
wherein an electrode material forming the gate electrode of the first planar field effect transistor cell extends from the gate electrode of the first planar field effect transistor cell to above the drain extension region of the second planar field effect transistor cell and forms there a field plate formed between the drain terminal and the gate electrode of the second planar field effect transistor cell, the semiconductor device further comprising:
a further dielectric laterally adjoining a gate dielectric of the first planar field effect transistor cell and formed vertically between the field plate and the drain extension region of the first planar field effect transistor cell, a thickness of the further dielectric being greater than a thickness of the gate dielectric of the first planar field effect transistor cell.

2. The semiconductor device of claim 1 , wherein the drain extension region is configured to block a drain-to-source voltage in a range of 5 V to 200 V.

3. The semiconductor device of claim 1 , further comprising:
a deep body region electrically connected to the source terminal and extending below the drain extension region of the first planar field effect transistor cell in a first lateral direction along a channel length direction of the channel region perpendicular to a channel width direction,
wherein the deep body region in the first lateral direction and the drain extension region in the first lateral direction at least partly overlap.

4. A semiconductor device, comprising:
a first planar field effect transistor cell comprising a drain extension region between a channel region and a drain terminal at a first surface of a semiconductor body; and
a second planar field effect transistor cell comprising a drain extension region between a channel region and a drain terminal at the first surface of the semiconductor body,
wherein a gate electrode of the first planar field effect transistor cell is electrically connected to a source terminal,
wherein the drain extension region of the first planar field effect transistor cell is configured to block a drain-to-source voltage in a range of 5 V to 200 V,
wherein a gate electrode of the second planar field effect transistor cell is connected to a gate terminal that is electrically isolated from the source terminal,
wherein the drain extension region of the second planar field effect transistor cell is configured to block a drain-to-source voltage in a range of 5 V to 200 V,
wherein an electrode material forming the gate electrode of the first planar field effect transistor cell extends from the gate electrode of the first planar field effect transistor cell to above the drain extension region of the second planar field effect transistor cell and forms there a field plate formed between the drain terminal and the gate electrode of the second planar field effect transistor cell, the semiconductor device further comprising:
a further dielectric laterally adjoining a gate dielectric of the first planar field effect transistor cell and formed vertically between the field plate and the drain extension region of the first planar field effect transistor cell, a thickness of the further dielectric being greater than a thickness of the gate dielectric of the first planar field effect transistor cell.

5. The semiconductor device of claim 4 , wherein a first thickness of the gate dielectric arranged on the channel region of the first planar field effect transistor cell is less than a second thickness of a second gate dielectric arranged on the channel region of the second planar field effect transistor cell.

6. The semiconductor device of claim 5 , wherein a ratio of the second thickness to the first thickness lies in a range of 2 to 20.

7. The semiconductor device of claim 4 , wherein a body region of the first planar field effect transistor cell and a body region of the second planar field effect transistor cell, from opposite sides, laterally adjoin a component isolation region formed between the first planar field effect transistor cell and the second planar field effect transistor cell.

8. The semiconductor device of claim 4 , wherein a first lateral direction extends along a channel length direction of the channel region perpendicular to a channel width direction, and wherein lateral dimensions of doped semiconductor regions of the first planar field effect transistor cell along the first lateral direction correspond to lateral dimensions of corresponding doped semiconductor regions of the second planar field effect transistor cell along the first lateral direction.

9. The semiconductor device of claim 4 , wherein an electrode material forming the gate electrode of the first planar field effect transistor cell extends from the gate electrode of the first planar transistor cell to above the drain extension region of the second planar field effect transistor cell and forms there a field plate formed between the drain terminal and the gate electrode of the second planar field effect transistor cell.

10. The semiconductor device of claim 4 , wherein the second planar field effect transistor cell is part of a lateral power transistor having a multiplicity of parallel-connected transistor cells that are configured for switching load currents of greater than 100 mA.

11. The semiconductor device of claim 4 , wherein a threshold voltage of the first planar field effect transistor cell is less than a forward voltage of a body-drain diode of the first planar field effect transistor cell.

12. The semiconductor device of claim 4 , wherein the further dielectric comprises a shallow trench isolation dielectric.

13. The semiconductor device of claim 12 , wherein the further dielectric between the shallow trench isolation dielectric and the gate dielectric of the first planar field effect transistor cell comprises a planar dielectric that is thicker than the gate dielectric.

14. The semiconductor device of claim 4 , wherein a part of the gate dielectric of the first planar field effect transistor cell at the first surface adjoins a top side of a part of the drain extension region.

15. The semiconductor device of claim 4 , wherein the further dielectric is a LOCOS (Local Oxidation of Silicon) oxide.

16. The semiconductor device of claim 4 , wherein the further dielectric is a planar dielectric, wherein an underside of the further dielectric transitions into an underside of the gate dielectric of the first planar field effect transistor cell without any steps, and wherein a top side of the further dielectric transitions into a top side of the gate dielectric of the first planar field effect transistor cell via a step directed toward the first surface.

17. The semiconductor device of claim 4 , wherein a thickness of the further dielectric increases in a direction toward the drain terminal, wherein an underside of the further dielectric extends parallel to the first surface, and wherein a top side of the further dielectric falls obliquely with respect to the

Assignees

• Infineon Technologies Ag

Inventors

• Meiser Andreas
• Kampen Christian

Classifications

• H10D64/514

  characterised by the insulating layers · CPC title

• H10D64/111

  Field plates · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D62/235

  of IGFETs (IGFETs having buried channels H10D30/637) · CPC title

• H10D62/116

  adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions · CPC title