Temperature based programming in memory

Patent metadata

Field	Value
Publication number	US-10984876-B2
Application number	US-201916445367-A
Country	US
Kind code	B2
Filing date	Jun 19, 2019
Priority date	Jun 19, 2019
Publication date	Apr 20, 2021
Grant date	Apr 20, 2021

Abstract

Various methods include receiving, by a controller, a temperature reading of a memory array, the temperature reading includes a temperature value; determining the temperature value is below a first threshold; in response, modifying a duration of a verify cycle of a write operation to create a modified verify cycle; then programming a first data into the memory array using the write operation that uses the modified verify cycle. Methods additionally include receiving a second temperature reading of the memory array, the second temperature reading includes a second temperature value; determining the second temperature value is below a second threshold, in response, decreasing the duration of a verify cycle of a verify cycle to create a second verify cycle, where the second verify cycle is shorter than the modified verify cycle; and then programming a second data into the memory array using the write operation that uses the second verify cycle.

First claim

What is claimed is:

1. A storage system, configured to modify clock parameters of a write operation, comprising:
a memory array; and
a controller coupled to the memory array, wherein the controller is configured to:
receive a temperature reading of the memory array, the temperature reading includes a temperature value;
determine the temperature value is below a first threshold; in response,
decrease a clock timing to a lower temperature timing, the clock timing associated with a write operation of the memory array; and then
program a first data into the memory array using the write operation that uses the lower temperature timing to decrease a duration of a verify cycle of the write operation.

2. The storage system of claim 1 , wherein the controller is further configured to:
receive a second temperature reading of the memory array, the second temperature reading including a second temperature value, wherein the second temperature value is lower than the temperature value;
determine the second temperature value is below a second threshold; in response,
further decrease the clock timing to a second lower temperature timing; and then
program a second data into the memory array using a write operation that uses the second lower temperature timing.

3. The storage system of claim 2 , wherein the temperature value is a first temperature value, and a difference between the first temperature value and the second temperature value is at least ten degrees Celsius.

4. The storage system of claim 1 , wherein the controller is further configured to:
receive a second temperature reading of the memory array, the second temperature reading including a second temperature value, wherein the second temperature value is higher than the temperature value;
determine the second temperature value is above the first threshold; in response,
increase the clock timing to a high temperature timing; and then
program a second data into the memory array using a write operation that uses the high temperature timing.

5. The storage system of claim 4 , wherein a duration of programming the second data is longer than a duration of programming the first data.

6. The storage system of claim 1 , further comprising:
performing a read operation; and
modifying a clock timing associated with the read operation based on the temperature value.

7. The storage system of claim 1 , wherein
the temperature value is a first temperature value that is lower than a second temperature value, and
a duration of programming the first data is lower than a duration of programming a second data into the memory array at the second temperature value.

8. The storage system of claim 7 , wherein a number of programming pulses used to program the first data is greater than a number of programming pulses used to program the second data.

9. A memory controller, comprising:
a first terminal configured to couple to a memory array,
the memory controller configured to:
receive a temperature reading of the memory array, the temperature reading includes a temperature value;
determine the temperature value is below a first threshold; in response,
decrease a clock timing to a lower temperature timing, the clock timing associated with a write operation of the memory array; and then
program a first data into the memory array using the write operation that uses the lower temperature timing to reduce a duration of a verify cycle of the write operation.

10. The memory controller of claim 9 , further configured to:
receive a second temperature reading of the memory array, the second temperature reading including a second temperature value, wherein the second temperature value is higher than the temperature value;
determine the second temperature value is above the first threshold; in response,
increase the clock timing to a high temperature timing; and then
program a second data into the memory array using a write operation that uses the high temperature timing.

11. The memory controller of claim 10 , wherein a duration of programming the second data is longer than a duration of programming the first data.

12. The memory controller of claim 10 , wherein a duration of programming the second data is the same as a duration of programming the first data.

13. The memory controller of claim 9 , wherein the controller is further configured to:
receive a second temperature reading of the memory array, the second temperature reading including a second temperature value, wherein the second temperature value is lower than the temperature value;
determine the second temperature value is below a second threshold; in response,
further decrease the clock timing to a second lower temperature timing; and then
program a second data into the memory array using a write operation that uses the second lower temperature timing.

14. The memory controller of claim 13 , wherein a duration of programming the second data is less than a duration of programming the first data.

15. The memory controller of claim 13 , where the temperature value is a first temperature value, and a difference between the first temperature value and the second temperature value is at least ten degrees Celsius.

16. The memory controller of claim 9 , further configured to store a set of clock timings, wherein:
a respective clock timing of the set of clock timings is associated with a first range of temperature values, and
another respective clock timing of the set of clock timings is associated with a second range of temperature values.

17. A method for dynamically adjusting clock parameters of a write operation, comprising:
receiving, by a controller, a temperature reading of a memory array, the temperature reading includes a temperature value;
determining the temperature value is below a first threshold; in response,
reducing a duration of a verify cycle of a write operation to create a modified verify cycle; and then
programming a first data into the memory array using the write operation that uses the modified verify cycle.

18. The method of claim 17 , further comprising,
prior to programming the first data into the memory array, modifying a duration of a programming cycle of the write operation based on the temperature value to create a modified programming cycle.

19. The method of claim 17 , further comprising:
receiving a second temperature reading of the memory array, the second temperature reading includes a second temperature value, wherein the second temperature value is lower than the temperature value;
determining the second temperature value is below a second threshold; in response,
decreasing the duration of a verify cycle of a write operation to create a second verify cycle, wherein the second verify cycle is shorter than the modified verify cycle; and then
programming a second data into the memory array using the write operation that uses the second verify cycle.

Assignees

• Sandisk Technologies Llc
• SanDiskTechnologies LLC

Inventors

• Dak Piyush
• Dunga Mohan
• Qin Chao
• Masuduzzaman Muhammad
• Yang Xiang

Classifications

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C16/3418

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/32 Primary

  Timing circuits · CPC title