Protection of a microcontroller

Patent metadata

Field	Value
Publication number	US-10984845-B2
Application number	US-201916729056-A
Country	US
Kind code	B2
Filing date	Dec 27, 2019
Priority date	Dec 28, 2018
Publication date	Apr 20, 2021
Grant date	Apr 20, 2021

Abstract

In an embodiment, a method for protecting an electronic circuit includes: detecting a malfunction of the electronic circuit; executing a plurality of waves of countermeasures without interrupting an operation of the electronic circuit; and triggering a reset of the electronic circuit after executing the plurality of waves of countermeasures. An interval between two waves of countermeasures of the plurality of waves of countermeasures is variable.

First claim

What is claimed is:

1. A method for protecting an electronic circuit, the method comprising:
detecting a malfunction of the electronic circuit;
in response to detecting the malfunction, executing a plurality of waves of countermeasures without interrupting an operation of the electronic circuit, wherein a first wave of countermeasures of the plurality of waves of countermeasures implements the step of blocking programming of a non-volatile memory of the electronic circuit, or the step of blocking an input or an output of the electronic circuit, or the step of regenerating a cryptographic key, wherein a second wave of countermeasures of the plurality of waves of countermeasures implement the step of generating a non-maskable interrupt of a program executed by the electronic circuit, and wherein an interval between the first and second waves of countermeasures is variable; and
triggering a reset of the electronic circuit after executing the plurality of waves of countermeasures.

2. The method of claim 1 , wherein a first group of waves of countermeasures of the plurality of waves of countermeasures does not comprise a non-maskable interrupt.

3. The method of claim 2 , wherein the first group of waves of countermeasures comprises:
blocking writing in a memory;
blocking all or a part of an output of the electronic circuit; or
regenerating cryptographic keys.

4. The method of claim 2 , wherein a second group of waves of countermeasures of the plurality of waves of countermeasures comprises a non-maskable interrupts.

5. The method of claim 1 , wherein the variable interval is random.

6. The method of claim 5 , wherein the variable interval is longer than a predetermined minimum time and shorter than a predetermined maximum time.

7. The method of claim 1 , wherein a number of countermeasures waves of the plurality of waves of countermeasures varies from one execution to another.

8. The method of claim 1 , wherein a number of countermeasures per wave of countermeasures of the plurality of waves of countermeasures varies from one execution to another.

9. The method of claim 1 , wherein the plurality of waves of countermeasures implement, at each detection of a malfunction of the electronic circuit, the steps of:
blocking programming of a non-volatile memory of the electronic circuit;
blocking an output of the of the electronic circuit;
after blocking programming and after blocking the output of the electronic circuit, waiting for a first duration;
after waiting for the first duration, generating a non-maskable interrupt of a program executed by the electronic circuit;
after generating the non-maskable interrupt, waiting for a second duration;
requesting the reset of the electronic circuit; and
requesting a deactivation of a main clock of the electronic circuit.

10. The method of claim 9 , wherein the first duration and the second duration are random.

11. The method of claim 10 , wherein the first and second durations are longer than a predetermined minimum duration and shorter than a predetermined maximum duration.

12. The method of claim 9 , wherein the electronic circuit is a microcontroller.

13. The method of claim 1 , further comprising requesting a deactivation of a main clock of the electronic circuit after generating the non-maskable interrupt.

14. The method of claim 1 , wherein the first wave of countermeasures implements the step of blocking programming of the non-volatile memory.

15. The method of claim 1 , further comprising, after generating the non-maskable interrupt, deleting a cryptographic key or emptying the non-volatile memory.

16. An electronic circuit comprising:
a detector configured to detect a malfunction;
a processing circuit configured to process signals supplied by the detector, and configured to execute, in response to the signals supplied by the detector, a plurality of waves of countermeasures without interrupting an operation of the electronic, circuit, wherein a first wave of countermeasures of the plurality of waves of countermeasures implements the step of blocking programming of a non-volatile memory of the electronic circuit, or the step of blocking an input or an output of the electronic circuit, or the step of regenerating a cryptographic key, wherein a second wave of countermeasures of the plurality of waves of countermeasures implement the step of generating a non-maskable interrupt of a program executed by the electronic circuit, and wherein an interval between the first and second waves of countermeasures is variable; and
a reset circuit configured to trigger a reset of the electronic circuit.

17. The electronic circuit of claim 16 , further comprising a second detector configured to detect a second malfunction, wherein the processing circuit is further configured to process signals supplied by the second detector and configured to execute, in response to the signals supplied by the second detector, the plurality of waves of countermeasures.

18. The electronic circuit of claim 16 , wherein a first group of waves of countermeasures of the plurality of waves of countermeasures does not comprise a non-maskable interrupt.

19. The electronic circuit of claim 18 , wherein the processing circuit is configured to, in the first group of waves of countermeasures:
block writing in a memory of the electronic circuit;
block all or a part of an output of the electronic circuit; or
regenerate cryptographic keys.

20. The electronic circuit of claim 18 , wherein a second group of waves of countermeasures of the plurality of waves of countermeasures comprises a non-maskable interrupts.

21. The electronic circuit of claim 16 , wherein the variable interval is random.

22. The electronic circuit of claim 16 , wherein a number of countermeasure waves of the plurality of waves of countermeasures varies from one execution to another.

23. The electronic circuit of claim 16 , wherein a number of countermeasures per wave of countermeasures of the plurality of waves of countermeasures varies from one execution to another.

24. The electronic circuit of claim 16 , wherein the processing circuit is configured to, at each detection of a malfunction:
block programming of a non-volatile memory of the electronic circuit;
block an output of the electronic circuit;
after blocking programming of the non-volatile memory and after blocking the output of the electronic circuit, wait for a first random duration;
after waiting for the first random duration generate a non-maskable interrupt of a program executed by the electronic circuit;
after generating the non-maskable interrupt, wait for a second random duration; and
after waiting for the second random duration, request the reset of the electronic circuit and request a deactivation of a main clock of the electronic circuit.

25. The electronic circuit of claim 16 , wherein the electronic circuit comprises a microcontroller.

26. A method comprising:
detecting a malfunction of an electronic circuit;
in response to detecting the malfunction, execute a first countermeasure without interrupting an operation of the electronic circuit, wherein the first countermeasure does not trigger a non-maskable interrupt, and wherein the first countermeasure implements the step of blocking programming of a non-volatile memory of the electronic circuit, or the step of blocking an input or an output of the electronic circuit, or the step of r

Assignees

• St Microelectronics Rousset
• St Microelectronics Alps Sas

Inventors

• Moisuc Diana
• Laurencin Christophe

Classifications

• G06F21/81 Primary

  by operating on the power supply, e.g. enabling or disabling power-on, sleep or resume operations · CPC title

• G06F21/77 Primary

  in smart cards · CPC title

• G11C16/22

  Safety or protection circuits preventing unauthorised or accidental access to memory cells · CPC title

• G11C8/20 Primary

  Address safety or protection circuits, i.e. arrangements for preventing unauthorized or accidental access · CPC title

• H04B3/52

  Systems for transmission between fixed stations via waveguides · CPC title