Multi-master hybrid bus apparatus

Patent metadata

Field	Value
Publication number	US-10983942-B1
Application number	US-201916710457-A
Country	US
Kind code	B1
Filing date	Dec 11, 2019
Priority date	Dec 11, 2019
Publication date	Apr 20, 2021
Grant date	Apr 20, 2021

Abstract

A multi-master hybrid bus apparatus is provided. The multi-master hybrid bus apparatus includes a hybrid bus bridge circuit configured to couple multiple master circuits with one or more slave circuits via heterogeneous communication buses. In examples discussed herein, the multiple master circuits can correspond to multiple physically separated master circuits or multiple bus ports provided in a single master circuit. In a non-limiting example, the hybrid bus bridge circuit is coupled to the multiple master circuits via multiple radio frequency front-end (RFFE) buses and to the slave circuits via at least one single-wire bus (SuBUS) consisting of a single wire. By bridging the multiple master circuits to the slave circuits based on a single hybrid bus bridge circuit, it may be possible to enable flexible heterogeneous bus deployment in an electronic device (e.g., a smartphone) with reduced cost and/or footprint.

First claim

What is claimed is:

1. A multi-master hybrid bus apparatus comprising:
at least one first primary bus and at least one second primary bus, wherein the at least one first primary bus is a same type of bus as the at least one second primary bus;
at least one auxiliary bus consisting of one wire, wherein the at least one auxiliary bus is a different type of bus from the at least one first primary bus and the at least one second primary bus; and
a hybrid bus bridge circuit comprising:
at least one first primary bus port coupled to the at least one first primary bus;
at least one second primary bus port coupled to the at least one second primary bus;
at least one auxiliary bus port coupled to the at least one auxiliary bus; and
a control circuit configured to:
receive at least one first primary bus command sequence and at least one second primary bus command sequence via the at least one first primary bus port and the at least one second primary bus port, respectively;
convert the at least one first primary bus command sequence and the at least one second primary bus command sequence into at least one first auxiliary bus command sequence and at least one second auxiliary bus command sequence, respectively; and
provide the at least one first auxiliary bus command sequence and the at least one second auxiliary bus command sequence to the at least one auxiliary bus port.

2. The multi-master hybrid bus apparatus of claim 1 further comprising:
at least one first master circuit coupled to the at least one first primary bus; and
at least one second master circuit coupled to the at least one second primary bus.

3. The multi-master hybrid bus apparatus of claim 1 further comprising at least one master circuit comprising:
at least one first master bus port coupled to the at least one first primary bus; and
at least one second master bus port coupled to the at least one second primary bus.

4. The multi-master hybrid bus apparatus of claim 1 wherein the control circuit is further configured to:
receive the at least one first primary bus command sequence and the at least one second primary bus command sequence concurrently;
convert the at least one first primary bus command sequence and the at least one second primary bus command sequence into the at least one first auxiliary bus command sequence and the at least one second auxiliary bus command sequence, respectively; and
provide the at least one first auxiliary bus command sequence and the at least one second auxiliary bus command sequence to the at least one auxiliary bus port based on a predefined priority among the at least one first primary bus port and the at least one second primary bus port.

5. The multi-master hybrid bus apparatus of claim 4 wherein the hybrid bus bridge circuit further comprises a first-in first-out (FIFO) queue configured to output the at least one first auxiliary bus command sequence and the at least one second auxiliary bus command sequence to the at least one auxiliary bus port, wherein the control circuit is further configured to enqueue the at least one first auxiliary bus command sequence and the at least one second auxiliary bus command sequence in the FIFO queue based on the predefined priority.

6. The multi-master hybrid bus apparatus of claim 4 wherein the control circuit is further configured to:
receive at least one first auxiliary data payload and at least one second auxiliary data payload via the at least one auxiliary bus port;
convert the at least one first auxiliary data payload and the at least one second auxiliary data payload into at least one first bus data payload and at least one second bus data payload, respectively; and
provide the at least one first bus data payload and the at least one second bus data payload to the at least one first primary bus port and the at least one second primary bus port, respectively.

7. The multi-master hybrid bus apparatus of claim 1 wherein:
the at least one auxiliary bus comprises at least one single-wire bus (SuBUS) consisting of the one wire;
the at least one first primary bus comprises at least one first radio frequency (RF) front-end (RFFE) bus; and
the at least one second primary bus comprises at least one second RFFE bus.

8. The multi-master hybrid bus apparatus of claim 7 further comprising at least one SuBUS slave circuit coupled to the at least one SuBUS and identified by at least one unique slave identification (USID).

9. The multi-master hybrid bus apparatus of claim 8 wherein:
the at least one SuBUS slave circuit comprises:
a transmit circuit configured to transmit an RF transmit signal via a first coupled antenna; and
a receive circuit configured to receive an RF receive signal via a second coupled antenna; and

the control circuit is further configured to:
receive at least one first RFFE command sequence for programming the transmit circuit via the at least one first primary bus port;
receive at least one second RFFE command sequence for programming the receive circuit via the at least one second primary bus port;
convert the at least one first RFFE command sequence and the at least one second RFFE command sequence into at least one first SuBUS command sequence and at least one second SuBUS command sequence, respectively; and
provide the at least one first SuBUS command sequence and the at least one second SuBUS command sequence to the transmit circuit and the receive circuit via the at least one auxiliary bus port, respectively.

10. The multi-master hybrid bus apparatus of claim 9 wherein the control circuit is further configured to:
receive at least one first SuBUS data payload and at least one second SuBUS data payload from the transmit circuit and the receive circuit, respectively;
convert the at least one first SuBUS data payload and the at least one second SuBUS data payload into at least one first RFFE data payload and at least one second RFFE data payload, respectively; and
provide the at least one first RFFE data payload and the at least one second RFFE data payload to the at least one first primary bus port and the at least one second primary bus port, respectively.

11. The multi-master hybrid bus apparatus of claim 8 wherein:
the at least one SuBUS slave circuit comprises:
a first transceiver circuit configured to communicate a first RF signal via a first coupled antenna; and
a second transceiver circuit configured to communicate a second RF signal via a second coupled antenna; and

the control circuit is further configured to:
receive at least one first RFFE command sequence configured for programming the first transceiver circuit via the at least one first primary bus port;
receive at least one second RFFE command sequence for programming the second transceiver circuit via the at least one second primary bus port;
convert the at least one first RFFE command sequence and the at least one second RFFE command sequence into at least one first SuBUS command sequence and at least one second SuBUS command sequence, respectively; and
provide the at least one first SuBUS command sequence and the at least one second SuBUS command sequence to the first transceiver circuit and the second transceiver circuit via the at least one auxiliary bus port, respectively.

12. The multi-master hybrid bus apparatus of claim 11 wherein the control circuit is further configured to:
receive at least one first SuBUS data payload and at least one second SuBUS data payload from the first transceiver circuit and the second transceiver circuit, respectively;
convert the at least one first SuBUS data payload and the at least one second SuBUS data payload into at least one first RFFE data p

Assignees

• Qorvo Us Inc

Inventors

• Ngo Christopher Truong
• Hietala Alexander Wayne

Classifications

• H04L69/08

  Protocols for interworking; Protocol conversion · CPC title

• H04L12/403

  with centralised control, e.g. polling · CPC title

• H04L12/40032

  Details regarding a bus interface enhancer · CPC title

• G06F13/4027 Primary

  using bus bridges (G06F13/4022 takes precedence) · CPC title

• H04L12/40163

  by assigning priority to messages according to a message field · CPC title