Scalable synthesis of signals of high symbol rate using lower symbol rate DSPS

Patent metadata

Field	Value
Publication number	US-10979270-B2
Application number	US-201916298455-A
Country	US
Kind code	B2
Filing date	Mar 11, 2019
Priority date	Mar 9, 2018
Publication date	Apr 13, 2021
Grant date	Apr 13, 2021

Abstract

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for transmitting signals with a high data rate. In some implementations, an apparatus includes a first digital signal processor outputting first data at a first data rate. A second digital signal processor outputting second data at a second data rate. A filter circuitry receiving and up-sampling the first and second data. Additionally, the apparatus includes a combiner circuit that receives the first up-sampled data and the second up-sampled data, the combiner circuit combining the first and second up-sampled data to provide a multiplexed output, the multiplexed output having a third data rate that is greater than the first data rate or the second data rate.

First claim

What is claimed is:

1. An apparatus, comprising:
a first digital signal processor operable to output first data at a first data rate;
a second digital signal processor operable to output second data at a second data rate;
filter circuitry operable to receive and up-sample the first and second data;
a combiner circuit that receives the first up-sampled data and the second up-sampled data, the combiner circuit combining the first and second up- sampled data to provide a multiplexed output, the multiplexed output having a third data rate that is greater than the first data rate or the second data rate; and
a transmitter comprising:
a plurality of path engines;
a gain-sharing module, wherein the gain-sharing module is connected to the plurality of path engines and each path engine of the plurality of path engines comprises:
the first digital signal processor configured to receive input data and output the first data at the first data rate; and
a digital-to-analog converter (DAC) configured to receive the multiplexed output from the combiner circuit and output analog representations of the multiplexed output;

the combiner circuit configured to receive the first data from the first digital signal processor and the second data from the second digital signal processor and output the multiplexed output; and
a modulator configured to generate a modulated output based on an analog representation of the multiplexed output.

2. The apparatus of claim 1 , further comprising:
a laser generating an optical signal; and
the modulator receiving the analog representation of the multiplexed output and the optical signal and modulating the optical signal based on the analog representation of the multiplexed output to generate a modulated optical signal that comprises a plurality of subcarriers.

3. The apparatus of claim 2 , wherein the plurality of path engines includes a first plurality of path engines and the gain-sharing module includes a first gain-sharing module, and further comprising:
a receiver, comprising:
a de-modulator configured to:
receive the plurality of subcarriers at the second data rate;
receive a local oscillator signal from a local oscillator;
combine the local oscillator signal and the plurality of subcarriers to generate a resulting signal; and
output the resulting signal to a detector;

the detector configured to provide a set of voltage signals based on the resulting signal;
a second plurality of path engines, wherein each path engine of the second plurality of path engines comprises:
an analog-to-digital converter (ADC), each ADC configured to receive the set of voltage signals from the detector and generate, using the set of voltage signals, digital representations of signals to provide to a de-multiplexer;
a receive digital signal processor configured to receive fourth subcarriers from the de-multiplexer at the first data rate and output digital data;
a de-interleaver configured to receive the digital data and output de-interleaved data; and
a forward error correction decoder configured to receive arranged de-interleaved data from a second gain-sharing module and output bit data;

and
the de-multiplexer that is configured to receive the digital representations of signals from each ADC in the plurality of second path engines and output the fourth subcarriers to each path engine of the second plurality of path engines.

4. The apparatus of claim 3 , further comprising:
a second gain-sharing module that is connected to the second plurality of path engines and is configured to:
receive the de-interleaved data output by the de-interleaver of each of the path engines of the second plurality of path engines; and
re-arrange the de-interleaved data according to a dispersing arrangement performed by the first gain-sharing module.

5. The apparatus of claim 1 , wherein each of the path engines further comprises:
a forward error correction encoder configured to receive the input data and output encoded data to the gain-sharing module; and
an interleaver configured to receive a split portion of the encoded data from the gain-sharing module and output interleaved data.

6. The apparatus of claim 5 , wherein the gain-sharing module is configured to:
receive the encoded data from the forward error correction encoder from each of the path engines of the plurality of path engines: and
disperse, according to a dispersing arrangement, the encoded data across the plurality of path engines, to the interleaver of each of the path engines of the plurality of path engines.

7. The apparatus of claim 1 , wherein the second data rate is a multiplicative factor of the first data rate and a number of the path engines from the plurality of path engines.

8. The apparatus of claim 7 , wherein the filter circuitry is configured to up-sample each subcarrier of the first data by a number equivalent to the number of the path engines.

9. The apparatus of claim 1 , wherein the combiner circuit further includes:
for each path engine in the plurality of path engines:
an up-sampling filter configured to shape a spectrum for each subcarrier of the first data;
a multiplier configured to multiply each subcarrier of the first data by a carrier frequency surrounding a frequency of the first data rate, such that each subcarrier of the multiplexed output occupies a non-overlapping frequency band; and

a summer configured to sum the output from each of the multipliers and output digital representations of the multiplexed output.

Assignees

• Infinera Corp

Inventors

• Sun Han
• Lemus Avid
• Awadalla Ahmed
• Wu Kuang-Tsan

Classifications

• H04J14/0298 Primary

  with sub-carrier multiplexing [SCM] · CPC title

• H04L27/26362

  Subcarrier weighting equivalent to time domain filtering, e.g. weighting per subcarrier multiplication (arrangements for removing intersymbol interference at the transmitter end H04L25/03343) · CPC title

• H04L27/2636

  with FFT or DFT modulators, e.g. standard single-carrier frequency-division multiple access [SC-FDMA] transmitter or DFT spread orthogonal frequency division multiplexing [DFT-SOFDM] · CPC title

• H04L5/001

  the frequencies being arranged in component carriers · CPC title

• H04L5/0008

  Wavelet-division · CPC title