Data acquisition system-in-package

Patent metadata

Field	Value
Publication number	US-10979062-B2
Application number	US-202016858099-A
Country	US
Kind code	B2
Filing date	Apr 24, 2020
Priority date	Dec 21, 2018
Publication date	Apr 13, 2021
Grant date	Apr 13, 2021

Abstract

This disclosure describes techniques to perform analog signal conditioning (including filtering and amplification) and analog-to-digital conversion (ADC) on a System-in-package (SIP) assembly technology. In particular, the disclosure combines a programmable gain amplifier (PGA), one or more filter circuits, and an ADC circuit onto the same SIP. These devices are coupled together on the SIP using high-accuracy and precise integrated-passive components. The SIP receives an analog signal, amplifies the analog signal with the PGA on the SIP, filters the amplified analog signal with the filter circuit(s) on the SIP, and then performs analog-to-digital conversion on the filtered amplified analog signal with the ADC circuit on the SIP. The SIP can be configured for various applications based on a variety of inputs and control mechanisms.

First claim

What is claimed is:

1. A data acquisition system-in-package (SIP) assembly, the SIP comprising:
an amplifier, enclosed on the SIP, configured to receive an analog input signal and to generate an amplified analog input signal; and
a resistor network, enclosed on the SIP and coupled to the amplifier, comprising first and second resistor components, wherein:
the first resistor component is partitioned into a first plurality of individual resistor components;
the second resistor component is partitioned into a second plurality of individual resistor components; and
the first plurality of individual resistor components is nested among the second plurality of individual resistor components, wherein a first individual resistor component of the second plurality of individual resistor components is physically located between a second individual resistor component of the first plurality of individual resistor components and a third individual resistor component of the first plurality of individual resistor components.

2. The SIP of claim 1 , further comprising:
a filter, enclosed on the SIP, configured to filter the amplified analog input signal, the filter being coupled to the amplifier via one or more wires bonded within the SIP, wherein the resistor network is configured to compensate for a resistance of the one or more wires.

3. The SIP of claim 1 , wherein the SIP is a land grid array (LGA), a ball grid array (BGA), or a pin grid array (PGA) package.

4. The SIP of claim 1 , wherein the first plurality of individual resistor components is configured in parallel with the second plurality of individual resistor components.

5. The SIP of claim 1 , wherein the resistor network comprises a third plurality of individual resistor components, wherein the third plurality of individual resistor components is configured in parallel with a first set of individual resistors of the first plurality of individual resistor components, and wherein the third plurality of individual resistor components is configured in series with a second set of individual resistors of the first plurality of individual resistor components.

6. The SIP of claim 1 , wherein the resistor network comprises integrated passive components that include at least one of a thin-film resistor network or a capacitor network.

7. The SIP of claim 1 , wherein the amplifier is implemented on a die comprising a first material of a set of materials and at least another amplifier implemented on the SIP is implemented on a die comprising a second material of the set of materials.

8. The SIP of claim 7 , wherein the set of materials comprises at least two of low-voltage MOS, high-voltage MOS, low-voltage DMOS, high-voltage DMOS, low-voltage bipolar, high-voltage bipolar, high-speed bipolar, BiCMOS, JFET, silicon germanium, silicon carbide, gallium nitride, gallium arsenide, gallium nitride on silicon carbide, gallium nitride on silicon, or semiconductor on insulator.

9. A method for using a system-in-package (SIP) assembly, the method comprising:
receiving, with an amplifier enclosed on the SIP, an analog input signal to generate an amplified analog input signal;
offsetting a resistance of one or more wires coupled to the amplifier with a resistor network, the resistor network comprising first and second plurality of individual resistor components enclosed on the SIP and coupled to the amplifier, wherein the first plurality of individual resistor components is nested among the second plurality of individual resistor components; and
generating, with an analog-to-digital converter (ADC) enclosed on the SIP, a digital representation of the amplified analog input signal.

10. The method of claim 9 , wherein a first individual resistor component of the second plurality of individual resistor components is physically located between a second individual resistor component of the first plurality of individual resistor components and a third individual resistor component of the first plurality of individual resistor components.

11. The method of claim 9 , wherein the first plurality of individual resistor components is configured in parallel with the second plurality of individual resistor components.

12. The method of claim 9 , wherein the SIP includes a third plurality of individual resistor components.

13. The method of claim 12 , wherein a sum of a resistance value of the third plurality of individual resistor components is smaller than a sum of a resistance value of the first plurality of individual resistor components, and wherein the sum of the resistance value of the third plurality of individual resistor components is smaller than a sum of a resistance value of the second plurality of individual resistor components.

14. The method of claim 13 , wherein a quantity of individual resistor components in the third plurality of individual resistor is larger than a quantity of individual resistor components in the first and second plurality of individual resistor components.

15. The method of claim 12 , wherein the third plurality of individual resistor components is configured in parallel with the first and second plurality of individual resistor components.

16. The method of claim 12 , wherein the third plurality of individual resistor components is configured in series with the first and second plurality of individual resistor components, and wherein the first and second plurality of individual resistor components are configured in parallel.

17. A method for configuring a system-in-package (SIP) assembly, the method comprising:
identifying first and second resistor components of a resistor network enclosed on the SIP and coupled to an amplifier enclosed on the SIP, the amplifier configured to receive an analog input signal and to generate an amplified analog input signal, wherein the SIP is a land grid array (LGA), a ball grid array (BGA), or a pin grid array (PGA) package;
partitioning the first resistor component into a first plurality of individual resistor components;
partitioning the second resistor component into a second plurality of individual resistor components; and
nesting the first plurality of individual resistor components among the second plurality of individual resistor components.

18. The method of claim 17 , further comprising compensating for a resistance of one or more wires bonded within the SIP with the resistor network.

19. The method of claim 17 , wherein nesting comprises physically placing a first individual resistor component of the second plurality of individual resistor components between a second individual resistor component of the first plurality of individual resistor components and a third individual resistor component of the first plurality of individual resistor components.

Assignees

• Analog Devices International Unlimited Co

Inventors

• Healy John P
• Hennessy Michael
• Ren Naiqian
• Mcguinness Patrick Martin
• Bombara Robert A

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W72/50

  Bond wires · CPC title

• H03F2203/45528

  the FBC comprising one or more passive resistors and being coupled between the LC and the IC · CPC title

• H03F3/45071

  with semiconductor devices only · CPC title

• H03M1/12 Primary

  Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title