Semiconductor structure

US10978575B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10978575-B2
Application numberUS-201916596953-A
CountryUS
Kind codeB2
Filing dateOct 9, 2019
Priority dateMar 21, 2017
Publication dateApr 13, 2021
Grant dateApr 13, 2021

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A semiconductor structure is provided and includes a substrate; a gate dielectric layer on the substrate; a dielectric barrier layer structure on the gate dielectric layer; a work function layer on the dielectric barrier layer structure; a gate barrier layer structure on the work function layer; and a gate electrode layer on the gate barrier layer structure. The dielectric barrier layer structure is doped with silicon and the gate barrier layer structure is doped with silicon.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor structure, comprising: a substrate; a gate dielectric layer on the substrate; a dielectric barrier layer structure on the gate dielectric layer, wherein the dielectric barrier layer structure is doped with silicon; a work function layer on the dielectric barrier layer structure; a gate barrier layer structure on the work function layer, wherein the gate barrier layer structure is doped with silicon; and a gate electrode layer on the gate barrier layer structure. 2. The structure according to claim 1 , wherein the dielectric barrier layer structure includes: a first dielectric barrier layer doped with silicon on the gate dielectric layer, and a second dielectric barrier layer on the first dielectric barrier layer. 3. The structure according to claim 1 , wherein: the first dielectric barrier layer has a thickness in a range of approximately from 20 Å to 40 Å. 4. The structure according to claim 2 , wherein: the first dielectric barrier layer is made of a material including silicon-doped titanium nitride. 5. The structure according to claim 2 , wherein: an atomic percentage concentration of silicon in the first dielectric barrier layer is in a range of approximately 5%-15%. 6. The structure according to claim 2 , wherein: the second dielectric barrier layer has a thickness in a range of approximately from 10 Å to 20 Å. 7. The structure according to claim 2 , wherein: the second dielectric barrier layer is made of a material including titanium nitride. 8. The structure according to claim 2 , wherein: the average atomic percentage concentration of silicon in the dielectric barrier layer structure is smaller than the average atomic percentage concentration of silicon in the first dielectric barrier layer. 9. The structure according to claim 1 , wherein: the gate dielectric layer is made of a material including hafnium oxide; and the gate electrode layer is made of a material including aluminum. 10. The structure according to claim 1 , wherein: a thickness of the dielectric barrier layer structure in a range of approximately from 30 Å to 60 Å. 11. The structure according to claim 1 , wherein: a thickness of the gate barrier layer structure is in a range of approximately from 30 Å to 60 Å. 12. The structure according to claim 1 , wherein the gate barrier layer structure includes: a first gate barrier layer on the work function layer, and a second gate barrier layer on the first gate barrier layer, wherein the second gate barrier layer is doped with silicon. 13. The structure according to claim 12 , wherein: a thickness of the first gate barrier layer is in a range of approximately from 10 Å to 20 Å. 14. The structure according to claim 12 , wherein: the first gate barrier layer is made of a material including titanium nitride. 15. The structure according to claim 12 , wherein: a thickness of the second gate barrier layer is in a range of approximately from 20 Å to 40 Å. 16. The structure according to claim 12 , wherein: the second gate barrier layer is made of a material including silicon-doped titanium nitride. 17. The structure according to claim 12 , wherein: an atomic percentage concentration of silicon in the second gate barrier layer is in a range of approximately 5%-15%. 18. The structure according to claim 12 , wherein: the dielectric barrier layer structure has a stacked structure and an average atomic percentage concentration of silicon in the dielectric barrier layer structure is smaller than an average atomic percentage concentration of silicon in a layer of the stacked structure adjacent to the work function layer. 19. The structure according to claim 12 , wherein: the gate barrier layer structure has stacked structures, and an average atomic percentage concentration of silicon in the gate barrier layer structure is smaller than an average atomic percentage concentration of silicon in the second gate barrier layer.

Assignees

Inventors

Classifications

  • using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329) · CPC title

  • the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

  • of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers · CPC title

  • in openings in dielectrics · CPC title

  • of isolation regions comprising dielectric materials · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US10978575B2 cover?
A semiconductor structure is provided and includes a substrate; a gate dielectric layer on the substrate; a dielectric barrier layer structure on the gate dielectric layer; a work function layer on the dielectric barrier layer structure; a gate barrier layer structure on the work function layer; and a gate electrode layer on the gate barrier layer structure. The dielectric barrier layer structu…
Who is the assignee on this patent?
Semiconductor Mfg Int Shanghai Corp, Semiconductor Mfg Int Beijing Corp
What technology area does this patent fall under?
Primary CPC classification H10D64/017. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 13 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 6 related publications on this page (citations in our corpus or others sharing the same primary CPC).