Antifuse array and method of forming antifuse using anodic oxidation

Patent metadata

Field	Value
Publication number	US-10978461-B2
Application number	US-201916656270-A
Country	US
Kind code	B2
Filing date	Oct 17, 2019
Priority date	Mar 31, 2014
Publication date	Apr 13, 2021
Grant date	Apr 13, 2021

Abstract

A method for forming an antifuse on a substrate is provided, which comprises: forming a first conductive material on the substrate; placing the first conductive material in an electrolytic solution; performing anodic oxidation on the first conductive material to form a nanowire made of the first conductive material and surrounded by a first dielectric material formed during the anodic oxidation and to form the antifuse on the nanowire; and forming a second conductive material on the antifuse to sandwich the antifuse between the first conductive material and the second conductive material.

First claim

What is claimed is:

1. A method comprising:
patterning a first protrusion over a substrate;
performing one or more iterations of anodic oxidation on the first protrusion, wherein after the performing the one or more iterations of anodic oxidation, the first protrusion comprises a first dielectric material surrounding a nanowire, the first dielectric material comprising a tapered recess at a top surface thereof, wherein a depth of the tapered recess measured in a first direction is greater at a center of the first dielectric material than a depth of the tapered recess measured in the first direction at edges of the first dielectric material; and
forming a gate over the tapered recess, wherein the first dielectric material comprises an antifuse extending between the nanowire and the gate.

2. The method of claim 1 , wherein after the performing the one or more iterations of anodic oxidation, the first protrusion has a first width in a top portion of the first protrusion, the first protrusion has a second width in a bottom portion of the first protrusion disclosed closer to the substrate than the top portion, and the first width is greater than the second width.

3. The method of claim 1 , wherein forming the gate comprises depositing a conductive material over the first dielectric material, and etching the conductive material to form the gate.

4. The method of claim 1 , further comprising etching the first dielectric material to form a first recess exposing the nanowire, and depositing a conductive material in the first recess and electrically coupled with the nanowire.

5. The method of claim 1 , wherein forming the gate forms a plurality of gates, wherein the first dielectric material comprises a plurality of antifuses, and wherein each of the antifuses of the plurality of antifuses extends between the nanowire and a respective gate of the plurality of gates.

6. The method of claim 1 , wherein the first protrusion comprises a semiconductor material prior to the performing the one or more iterations of anodic oxidation on the first protrusion, wherein the first dielectric material comprises an oxide of the semiconductor material.

7. The method of claim 1 , wherein the first protrusion comprises a metal prior to the performing the one or more iterations of anodic oxidation on the first protrusion, wherein the first dielectric material comprises an oxide of the metal.

8. The method of claim 1 , wherein the gate is formed having a longitudinal axis perpendicular to a longitudinal axis of the nanowire.

9. A method comprising:
forming a protrusion on a substrate;
forming a first dielectric material surrounding a nanowire in the protrusion, wherein the forming the first dielectric material comprises oxidizing the protrusion, wherein the first dielectric material is a single, continuous material, and wherein a width of a top portion of the protrusion distal the substrate in a direction parallel to a major surface of the substrate is greater than a width of a bottom portion of the protrusion proximal the substrate in the direction parallel to the major surface of the substrate;
etching the first dielectric material to expose the nanowire;
depositing a conductive layer over the first dielectric material, wherein the conductive layer extends to make contact with the nanowire; and
etching the conductive layer to form at least one program line, wherein the first dielectric material comprises an antifuse interposed between the program line and the nanowire.

10. The method of claim 9 , wherein the etching the conductive layer forms a plurality of program lines comprising the at least one program line.

11. The method of claim 9 , wherein the oxidizing the protrusion comprises applying a non-uniform electric field to the protrusion to cause non-uniform anodic oxidation of the protrusion.

12. The method of claim 9 , wherein after the forming the first dielectric material, a first height of the first dielectric material at edges of the first dielectric material in a first direction perpendicular to the major surface of the substrate is greater than a second height of the first dielectric material at a center of the first dielectric material in the first direction, the first height and the second height being measured between the major surface of the substrate and top surfaces of the first dielectric material.

13. The method of claim 9 , wherein the depositing the conductive layer comprises depositing a metal using a charged-ion beam.

14. The method of claim 9 , wherein the forming the first dielectric material surrounding the nanowire forms the antifuse of a material having a dielectric strength from 10 MV/m to 1000 MV/m.

15. A method comprising:
patterning a protrusion over a substrate;
anodically oxidizing the protrusion to form a select line surrounded by a dielectric material, the dielectric material comprising an antifuse disposed over the select line in a direction perpendicular to a major surface of the substrate, the dielectric material comprising a single, continuous material in contact with a top surface, a bottom surface, and side surfaces of the select line;
etching the dielectric material to expose at least a portion of the select line; and
depositing a conductive material over the dielectric material, the conductive material being electrically coupled to the select line.

16. The method of claim 15 , further comprising etching the conductive material to form a program line, the program line being disposed over the antifuse in the direction perpendicular to the major surface of the substrate, the program line being discontinuous with a remainder of the conductive material.

17. The method of claim 15 , wherein the patterning the protrusion forms two terminal portions of the protrusion having first widths in a direction parallel with the major surface of the substrate and a central portion of the protrusion extending between the two terminal portions of the protrusion, the central portion of the protrusion having a second width in the direction parallel with the major surface of the substrate, the second width being less than the first widths.

18. The method of claim 17 , wherein the etching the dielectric material exposes portions of the select line in the two terminal portions of the protrusion, the exposed portions of the select line comprising a source and a drain.

19. The method of claim 15 , wherein after the anodically oxidizing the protrusion, the protrusion has a first height measured in a first direction perpendicular to the major surface of the substrate at edges of the protrusion and a second height measured in the first direction perpendicular to the major surface of the substrate at a center of the protrusion, the second height being less than the first height, the first height and the second height being measured between the major surface of the substrate and top surfaces of the protrusion.

20. The method of claim 9 , wherein the etching the conductive layer forms a plurality of program lines comprising the at least one program line, wherein the first dielectric material comprises an antifuse array comprising the antifuse, and wherein respective antifuses of the antifuse array are interposed between respective program lines of the plurality of program lines and the nanowire.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Univ Nat Taiwan

Inventors

• Hwu Jenn-Gwo
• Tian Wei-Cheng
• Pan Samuel C
• Wang Chao-Hsiung
• Liu Chi-Wen

Classifications

• H10P14/6324

  Formation by anodic treatments, e.g. anodic oxidation · CPC title

• H10W20/0554

  of nanotubes or nanowires · CPC title

• H10W20/065

  by making at least a portion of the conductive part non-conductive, e.g. by oxidation · CPC title

• H10W20/031

  of conductive parts of the interconnections · CPC title

• H10W20/491 Primary

  Antifuses, i.e. interconnections changeable from non-conductive to conductive · CPC title