Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-10978397-B2
Application number	US-201916707294-A
Country	US
Kind code	B2
Filing date	Dec 9, 2019
Priority date	Aug 8, 2016
Publication date	Apr 13, 2021
Grant date	Apr 13, 2021

Abstract

A semiconductor memory device includes word lines extending in a first direction on a semiconductor substrate, bit line structures crossing over the word lines and extending in a second direction intersecting the first direction, and contact pad structures between the word lines and between the bit line structures in plan view. A spacer structure extends between the bit line structures and the contact pad structures. The spacer structure includes a first air gap extending in the second direction along sidewalls of the bit line structures and a second air gap surrounding each of the contact pad structures and coupled to the first air gap.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
word lines extending in a first direction in a semiconductor substrate;
a bit line contact pattern;
bit line structures on the bit line contact pattern, the bit line structures crossing over the word lines and extending in a second direction intersecting the first direction;
bit line spacer structures on sidewalls of the bit line structures;
contact conductive pads arranged in a row between the bit line structures in plan view; and
insulating patterns between the contact conductive pads and between the bit line structures,
wherein top surfaces of the word lines are lower than a top surface of the semiconductor substrate,
wherein a bottom surface of the bit line contact pattern is lower than the top surface of the semiconductor substrate,
wherein a bottom surface of the contact conductive pad is lower than the top surface of the semiconductor substrate and is higher than the bottom surface of the bit line contact pattern,
wherein each of the bit line structures comprises a polysilicon pattern, a silicide pattern, a metal pattern, and a hard mask pattern, and
wherein each of the bit line spacer structures comprises:
a first spacer directly on the sidewalls of the bit line structures and extending along the bit line structures in the second direction;
a second spacer extending parallel with the first spacer in the second direction, the second spacer having a topmost surface lower than a topmost surface of the first spacer and higher than a topmost surface of the metal pattern of the bit line structure;
a first air gap between the first spacer and the second spacer extending in the second direction;
a third spacer above the second spacer; and
a second air gap extending from the first air gap to between the first spacer and the third spacer.

2. The device of claim 1 , wherein the first air gaps of the bit line spacer structures are parallel to each other.

3. The device of claim 1 , wherein the first air gap comprises first portions adjacent to the contact conductive pads and second portions adjacent to the insulating patterns, and
wherein a height of the first air gap is greater at the second portions than at the first portions.

4. The device of claim 1 , wherein the first air gap has a first width and the second air gap has a second width smaller than the first width.

5. The device of claim 1 , further comprising a landing pad connected to a respective one of the contact conductive pads,
wherein an upper portion of the landing pad partially overlaps with a portion of a respective one of the bit line structures, and
wherein an upper width of the landing pad is greater than a distance between adjacent ones of the bit line structures.

6. The device of claim 5 , wherein the first air gap includes first portions adjacent to the contact conductive pads and second portions adjacent to the insulating patterns, and
wherein the first portion of the first air gap and a portion of the second air gap overlap with the landing pad in plan view.

7. The device of claim 1 , wherein the third spacer has a ring shape surrounding a respective one of the contact conductive pads in a plan view.

8. The device of claim 7 , wherein the second air gap couples two adjacent ones of the first air gaps.

9. A semiconductor memory device, comprising:
word lines extending in a first direction in a semiconductor substrate;
bit line structures crossing over the word lines and extending in a second direction intersecting the first direction, each of the bit line structures comprising a polysilicon pattern, a silicide pattern, a metal pattern, and a hard mask pattern;
bit line spacer structures on sidewalls of the bit line structures;
contact conductive pads arranged in a row between the bit line structures in plan view; and
insulating patterns between the contact conductive pads and between the bit line structures; and
wherein each of the bit line spacer structures comprises:
a first spacer directly on the sidewalls of the bit line structures and extending along the bit line structures in the second direction;
a second spacer extending parallel with the first spacer in the second direction,
a third spacer above the second spacer; and
a first air gap between the first spacer and the second spacer extending in the second direction,

wherein a topmost surface of the second spacer is lower than a topmost surface of the first spacer and higher than a topmost surface of the metal pattern of the bit line structure.

10. The device of claim 9 , wherein each of the bit line spacer structures further comprises a second air gap extending from the first air gap to between the first spacer and the third spacer.

11. The device of claim 10 , wherein the second air gap surrounds a respective one of the contact conductive pads in plan view.

12. The device of claim 10 , wherein the first air gap has a first width and the second air gap has a second width smaller than the first width.

13. The device of claim 9 , wherein the first air gap comprises first portions adjacent to the contact conductive pads and second portions adjacent to the insulating patterns, and
wherein a height of the first air gap is greater at the second portions than at the first portions.

14. The device of claim 9 , further comprising a landing pad connected to a respective one of the contact conductive pads,
wherein an upper portion of the landing pad partially overlaps with a portion of a respective one of the bit line structures, and
wherein an upper width of the landing pad is greater than a distance between adjacent ones of the bit line structures.

15. The device of claim 9 , wherein the third spacer has a ring shape surrounding a respective one of the contact conductive pads in a plan view.

16. The device of claim 9 , wherein the first air gap continuously extends along the sidewalls of the bit line structures.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Eunjung
• Kim Hui-Jung
• Kim Keunnam
• Kim Daeik
• Kim Bong-Soo
• Hwang Yoosang

Classifications

• H10W20/495

  Capacitive arrangements or effects of, or between wiring layers · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W10/021 Primary

  of air gaps · CPC title

• H10W10/20

  Air gaps · CPC title