Shift register unit, method of driving the same, gate driving circuit and display device

Patent metadata

Field	Value
Publication number	US-10978168-B2
Application number	US-201916640201-A
Country	US
Kind code	B2
Filing date	Aug 5, 2019
Priority date	Aug 13, 2018
Publication date	Apr 13, 2021
Grant date	Apr 13, 2021

Abstract

A shift register unit, a method of driving the same, a gate driving circuit and a display device are provided. The shift register unit includes a pull-up node control circuit, a first pull-down node control circuit, a second pull-down node control circuit, a pull-down node switching control circuit, and a gate driving output circuit. The pull-down node switching control circuit is configured to control the first control voltage signal to be written into the first pull-down node and control the second control voltage signal to be written into the second pull-down node under the control of a frame reset control signal. The gate driving output circuit is configured to control a gate driving signal outputted by a gate driving signal output terminal under the control of the voltage signal of the pull-up node, the voltage signal of the first pull-down node, and the voltage signal of the second pull-down node.

First claim

What is claimed is:

1. A shift register unit, comprising:
a pull-up node control circuit, a first pull-down node control circuit, a second pull-down node control circuit, a pull-down node switching control circuit, and a gate driving output circuit, wherein
the pull-up node control circuit is configured to control a potential at a pull-up node;
the first pull-down node control circuit is configured to control a potential at a first pull-down node under the control of a voltage signal of the pull-up node and a first control voltage signal;
the second pull-down node control circuit is configured to control a potential at a second pull-down node under the control of the voltage signal of the pull-up node and a second control voltage signal;
the pull-down node switching control circuit is configured to control the first control voltage signal to be written into the first pull-down node and control the second control voltage signal to be written into the second pull-down node under the control of a frame reset control signal; and
the gate driving output circuit is configured to control a gate driving signal outputted by a gate driving signal output terminal under the control of the voltage signal of the pull-up node, the voltage signal of the first pull-down node, and the voltage signal of the second pull-down node,
wherein the first pull-down node control circuit is connected to the first pull-down node, the pull-up node, the first voltage terminal, and a first control voltage terminal, the first control voltage terminal is used to input the first control voltage signal;
the second pull-down node control circuit is connected to a second pull-down node, the pull-up node, the first voltage terminal, and a second control voltage terminal, the second control voltage terminal is used to input the second control voltage signal;
the pull-down node switching control circuit is connected to a frame reset control terminal, the first pull-down node, the second pull-down node, the first control voltage terminal and the second control voltage terminal, and controls the first pull-down node to be connected to the first control voltage terminal to write the first control voltage signal into the first pull-down node, and controls the second pull-down node to be connected to the second control voltage terminal to write the second control voltage signal into the second pull-down node under the control of the frame reset control signal, the frame reset control terminal is used to input the frame reset control signal; and
the gate driving output circuit is connected to the pull-up node, the first pull-down node, the second pull-down node, a gate driving signal output terminal, a clock signal terminal, and the first voltage terminal, and configured to control the gate driving signal output terminal to be connected to the clock signal terminal under the control of the voltage signal of the pull-up node, so as to output the clock signal to the gate driving signal output terminal, and control the gate driving signal outputted from the gate driving signal output terminal under the control of the voltage signal of the first pull-down node and the voltage signal of the second pull-down node, the clock signal terminal is used to input the clock signal.

2. The shift register unit according to claim 1 , wherein the pull-up node control circuit is configured to control the first voltage signal to be written into the pull-up node under the control of a frame reset control signal, control a potential at the pull-up node under the control of an input signal and a reset signal, and control the first voltage signal to be written into the pull-up node under the control of the first pull-down node or the second pull-down node;
the pull-up node control circuit is further configured to control the potential at the pull-up node to be a second voltage under the control of the input signal, and control the first voltage signal to be written into the pull-up node under the control of the reset signal.

3. The shift register unit according to claim 2 , wherein the pull-up node control circuit is connected to the frame reset control terminal, the input terminal, the reset terminal, the first pull-down node, the second pull-down node, the pull-up node and the first voltage terminal;
the pull-up node control circuit is configured to control the pull-up node to be connected to the first voltage terminal under the control of a frame reset control signal, so as to control the first voltage signal to be written into the pull-up node PU; control the potential at the pull-up node to a second voltage under the control of an input signal; control the pull-up node to be connected to the first voltage terminal under the control of a reset signal, so as to write the first voltage signal into the pull-up node; and control the first voltage signal to be written into the pull-up node under the control of the first pull-down node or the second pull-down node;
the first voltage terminal is used to input the first voltage signal; and
the input terminal is used to input the input signal, and the reset terminal is used to input the reset signal.

4. The shift register unit according to claim 1 , further comprising a carry output circuit, wherein
the carry output circuit is connected to the pull-up node, the first pull-down node, the second pull-down node, a carry signal output terminal, a clock signal terminal, and a first voltage terminal, and configured to control a clock signal to be outputted to a carry signal output terminal under the control of the voltage signal of the pull-up node; and control the carry signal outputted from the carry signal output terminal under the control of the voltage signal of the first pull-down node and the voltage signal of the second pull-down node.

5. The shift register unit according to claim 1 , wherein the pull-down node switching control circuit comprises:
a first switching control transistor, a control electrode thereof connected to the frame reset control terminal, a first electrode thereof connected to the first control voltage terminal, and a second electrode thereof connected to the first pull-down node; and
a second switching control transistor, a control electrode thereof connected to the frame reset control terminal, and a first electrode thereof connected to a second control voltage terminal, and a second electrode thereof connected to the second pull-down node.

6. The shift register unit according to claim 1 , wherein the pull-up node control circuit comprises:
an input transistor, a control electrode and a first electrode thereof connected to the input terminal, and a second electrode thereof connected to the pull-up node;
a reset transistor, a control electrode thereof connected to the reset terminal, a first electrode thereof connected to the pull-up node, and a second electrode thereof connected to the first voltage terminal;
a frame reset control transistor, a control electrode thereof connected to the frame reset control terminal, a first electrode thereof connected to the pull-up node, and a second electrode thereof connected to the first voltage terminal;
a first pull-up node noise reduction transistor, a control electrode thereof connected to the first pull-down node, a first electrode thereof connected to the pull-up node, and a second electrode thereof connected to the first voltage terminal; and
a second pull-up node noise reduction transistor, a control electrode thereof connected to the second pull-down node, a first electrode thereof connected to the pull-up node, and a second electrode thereof connected to the first voltage terminal;
the input terminal is used to input the input signal, the reset terminal is used to input the reset signal, the frame reset control terminal is used to input

Assignees

• Hefei Xinsheng Optoelectronics Technology Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Yang Tong
• Xie Yongxian

Classifications

• G11C19/28 Primary

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G3/36

  using liquid crystals · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title