Gate select signal with reduced interference

Patent metadata

Field	Value
Publication number	US-10977980-B2
Application number	US-202017036755-A
Country	US
Kind code	B2
Filing date	Sep 29, 2020
Priority date	Jun 11, 2019
Publication date	Apr 13, 2021
Grant date	Apr 13, 2021

Abstract

A processing system for a display device comprises a display driver configured to generate a gate select signal and output the gate select signal to gate select control circuitry to be driven on gate lines for display updating. The gate select signal comprises a transition from a first voltage to a second voltage, a transition from the second voltage to a third voltage, and a transition from the third voltage to the first voltage. The second voltage is greater than the first voltage and the second voltage is maintained for a first period. The third voltage is greater than the second voltage and the third voltage is maintained for a second period. The gate select signal is driven by the gate select control circuitry on gate lines of the display device to select one or more subpixels of the display device for display updating.

First claim

What is claimed is:

1. A processing system comprising:
driver circuitry configured to:
generate a gate select signal comprising a rising edge and a falling edge, wherein one or both of the rising edge and the falling edge comprises at least three voltage transitions; and
output the gate select signal to gate control circuitry configured to drive the gate select signal on a gate line of a display device for display updating.

2. The processing system of claim 1 , wherein the rising edge comprises at least three voltage transitions and the falling edge has less than three voltage transitions.

3. The processing system of claim 1 , wherein the falling edge comprises at least three voltage transitions and the rising edge has less than three voltage transitions.

4. The processing system of claim 1 , wherein each of the rising edge and the falling edge comprises at least three voltage transitions.

5. The processing system of claim 1 , wherein the voltage transitions of the rising edge comprise:
a first voltage transition from a first voltage to a second voltage; and
a second voltage transition from the second voltage to a third voltage, wherein the third voltage is greater than the second voltage and the second voltage is greater than the first voltage, wherein the voltage transitions of the falling edge comprises:
a third transition from the third voltage to a fourth voltage, and the fourth voltage is less than the third voltage and greater than the first voltage.

6. The processing system of claim 5 , wherein the fourth voltage is greater than or less than the second voltage.

7. The processing system of claim 5 , wherein the second voltage is driven during a first period and the fourth voltage is driven during a second period, wherein a length of the first period differs from a length of the second period.

8. A method for generating a gate select signal, the method comprising:
generating the gate select signal comprising a rising edge and a falling edge, wherein one or both of the rising edge and the falling edge comprises at least three voltage transitions; and
outputting the gate select signal to gate control circuitry configured to drive the gate select signal on a gate line of a display device for display updating.

9. The method of claim 8 , wherein the rising edge comprises at least three voltage transitions and the falling edge has less than three voltage transitions.

10. The method of claim 8 , wherein the falling edge comprises at least three voltage transitions and the rising edge has less than three voltage transitions.

11. The method of claim 8 , wherein each of the rising edge and the falling edge comprises at least three voltage transitions.

12. The method of claim 8 , wherein the voltage transitions of the rising edge comprise:
a first voltage transition from a first voltage to a second voltage; and
a second voltage transition from the second voltage to a third voltage, wherein the third voltage is greater than the second voltage, and the second voltage is greater than the first voltage, wherein the voltage transitions of the falling edge comprises:
a third transition from the third voltage to a fourth voltage, and wherein the fourth voltage is less than the third voltage and greater than the first voltage.

13. The method of claim 12 , wherein the fourth voltage is greater than or less than the second voltage.

14. The method of claim 12 , wherein the second voltage is driven during a first period and the fourth voltage is driven during a second period, wherein a length of the first period differs from a length of the second period.

15. A display device comprising:
gate lines;
gate control circuitry coupled to the gate lines; and
display driver circuitry coupled to the gate control circuitry and configured to:
generate a gate select signal comprising a rising edge and a falling edge, wherein one or both of the rising edge and the falling edge comprises at least three voltage transitions; and
output the gate select signal to gate control circuitry configured to drive the gate select signal on a gate line of the gate lines for display updating.

16. The display device of claim 15 , wherein the rising edge comprises at least three voltage transitions and the falling edge has less than three voltage transitions.

17. The display device of claim 15 , wherein the falling edge comprises at least three voltage transitions and the rising edge has less than three voltage transitions.

18. The display device of claim 15 , wherein each of the rising edge and the falling edge comprises at least three voltage transitions.

19. The display device of claim 15 , wherein the voltage transitions of the rising edge comprise:
a first voltage transition from a first voltage to a second voltage; and
a second voltage transition from the second voltage to a third voltage, wherein the third voltage is greater than the second voltage, and the second voltage is greater than the first voltage, wherein the voltage transitions of the falling edge comprises:
a third transition from the third voltage to a fourth voltage, wherein the fourth voltage is less than the third voltage and greater than the first voltage, and wherein the fourth voltage is greater than or less than the second voltage.

20. The display device of claim 15 , wherein the voltage transitions of the rising edge comprise:
a first voltage transition from a first voltage to a second voltage; and
a second voltage transition from the second voltage to a third voltage, wherein the third voltage is greater than the second voltage, and the second voltage is greater than the first voltage, the second voltage is driven during a first period, wherein the voltage transitions of the falling edge comprises:
a third transition from the third voltage to a fourth voltage, wherein the fourth voltage is less than the third voltage and greater than the first voltage, and wherein the fourth voltage is driven during a second period, wherein a length of the first period differs from a length of the second period.

Assignees

• Synaptics Inc

Inventors

• Shepelev Petr

Classifications

• H03K4/02

  having stepped portions, e.g. staircase waveform · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G3/3266

  Details of drivers for scan electrodes · CPC title